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| BU-6174X/6184X/6186X ENHANCED MINIATURE ADVANCED COMMUNICATIONS ENGINE [ENHANCED MINI-ACE/-ACE (MICRO-ACE)] FEATURES Make sure the next Card you purchase has... (R) * Fully Integrated 1553A/B Notice 2, McAir, STANAG 3838 Interface Terminal * Compatible with Mini-ACE (Plus) and ACE Generations * Choice of : - RT or BC/RT/MT In Same Footprint - RT or BC/RT/MT with 4K RAM - BC/RT/MT with 64K RAM, and RAM parity * Choice of 5V or 3.3V Logic * Package Options: - 1" Square Ceramic Flat Pack or Gull Wing - 0.815" Square BGA (-ACE) DESCRIPTION The Enhanced Miniature Advanced Communications Engine (Enhanced Mini-ACE) and -ACE (Micro-ACE) family of MIL-STD-1553 terminals provide complete interfaces between a host processor and a 1553 bus, and integrate dual transceiver, protocol logic, and 4K or 64K words of RAM. At 0.815" square, the -ACE (BGA package) option provides the smallest footprint in the industry. The terminals are powered by a choice of 5V or 3.3V logic. Multiprotocol support of MIL-STD-1553A/B and STANAG 3838, including versions incorporating McAir compatible transmitters, is provided. There is a choice of 10, 12, 16, or 20 MHz clocks. The BC/RT/MT versions with 64K words of RAM include built-in RAM parity checking. BC features include a built-in message sequence control engine, with a set of 20 instructions. This feature provides an autonomous means of implementing multi-frame message scheduling, message retry schemes, data double buffering, asynchronous message insertion, and reporting to the host CPU. The Enhanced Mini-ACE/-ACE incorporates a fully autonomous built-in self-test, providing comprehensive testing of the internal protocol logic and/or RAM. The RT offers the same choices of subaddress buffering as the ACE and Mini-ACE (Plus), along with a global circular buffering option, 50% rollover interrupt for circular buffers, an interrupt status queue, and an "Auto-boot" option to support MIL-STD-1760. The terminals provide the same flexibility in host interface configurations as the ACE/Mini-ACE, along with a reduction in the host processor's worst case holdoff time. Most software features are compatible with the previous generations of the Mini-ACE (Plus) and ACE series. * 5V Transceiver with 1760 and McAir Compatible Options * Comprehensive Built-In Self-Test * Flexible Processor/Memory Interface, with Reduced Host Wait Time * Choice of 10, 12, 16, or 20 MHz Clock * Highly Autonomous BC with Built-In Message Sequence Control: - Frame Scheduling - Branching - Asynchronous Message Insertion - General Purpose Queue - User-defined Interrupts * Advanced RT Functions - Global Circular Buffering - Interrupt Status Queue - 50% Circular Buffer Rollover Interrupts * Selective Message Monitor - Selection by Address, T/R Bit, Subaddress - Command and Data Stacks - 50% and 100% Stack Rollover Interrupts FOR MORE INFORMATION CONTACT: -ACE Data Device Corporation 105 Wilbur Place Bohemia, New York 11716 631-567-5600 Fax: 631-567-7358 www.ddc-web.com Technical Support: 1-800-DDC-5757 ext. 7771 (c) 2000 Data Device Corporation Data Device Corporation www.ddc-web.com CH. A CH. B TX/RX_A SHARED RAM (1) TRANSCEIVER A DATA BUFFERS PROCESSOR DATA BUS TX/RX_A DATA BUS DUAL ENCODER/DECODER, MULTIPROTOCOL AND MEMORY MANAGEMENT D15-D0 TX/RX_B ADDRESS BUS ADDRESS BUFFERS A15-A0 PROCESSOR ADDRESS BUS TRANSCEIVER B 2 TX/RX_B PROCESSOR AND MEMORY INTERFACE LOGIC TRANSPARENT/BUFFERED, STRBD, SELECT, RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN, MSB/LSB/DTGRT IOEN, READYD ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR, 8/16-BIT/DTREQ, POLARITY_SEL/DTACK INT PROCESSOR AND MEMORY CONTROL INTERRUPT REQUEST RT ADDRESS RTAD4-RTAD0, RTADP INCMD/MCRST, INCMD(2), MCRST(2) MISCELLANEOUS CLK_IN, TAG_CLK(2), MSTCLR, SSFLAG/EXT_TRG, TX-INH_A, TX-INH_B, UPADDREN, RSBITEN(2) NOTE 1: See Ordering Information for Available Memory Options. NOTE 2: Indicates signals brought out only on -ACE (BGA package) version. BU-6174X/6184X/6186X M-12/04-0 FIGURE 1. ENHANCED MINIATURE ADVANCED COMMUNICATIONS ENGINE BLOCK DIAGRAM TABLE 1. ENHANCED MINI-ACE/-ACE SERIES SPECIFICATIONS PARAMETER ABSOLUTE MAXIMUM RATING Supply Voltage * Logic +5V or +3.3V * RAM +5V * Transceiver +5V (Note 12) Logic * Voltage Input Range for +5V Logic (BU-61XX0/5) * Voltage Input Range for +3.3V Logic (BU-61XX0/3/5) RECEIVER Differential Input Resistance (Notes 1-6) Differential Input Capacitance (Notes 1-6) Threshold Voltage, Transformer Coupled, Measured on Stub Common Mode Voltage (Note 7) TRANSMITTER Differential Output Voltage * Direct Coupled Across 35 , Measured on Bus * Transformer Coupled Across 70 , Measured on Bus (BU-61XXXXX-XX0, BU-61XXXXX-XX2) (Note 13) Output Noise, Diff (Direct Coupled) Output Offset Voltage, Transformer Coupled Across 70 ohms Rise/Fall Time (BU-61XXXX3, BU-61XXXX4) LOGIC VIH All signals except CLK_IN CLK_IN VIL All signals except CLK_IN CLK_IN Schmidt Hysteresis All signals except CLK_IN CLK_IN IIH, IIL All signals except CLK_IN IIH (Vcc=5.25V, VIN=Vcc) IIH (Vcc=5.25V, VIN=2.7V) IIH (Vcc=3.6V, VIN=Vcc) IIH (Vcc=3.6V, VIN=2.7V) IIL (Vcc=5.25V, VIN=0.4V) IIL (Vcc=3.6V, VIN=0.4V) CLK_IN IIH IIL VOH (Vcc=4.5V, VIH=2.7V, VIL=0.2V, IOH=max) VOH (Vcc=3.0V, VIH=2.7V, VIL=0.2V, IOH=max) VOL (Vcc=4.5V, VIH=2.7V, VIL=0.2V, IOL=max) VOL (Vcc=3.0V, VIH=2.7V, VIL=0.2V, IOL=max) IOL (Vcc=4.5V) IOH (Vcc=4.5V) IOL (Vcc=3.0V) IOH (Vcc=3.0V) MIN TYP MAX UNITS TABLE 1. ENHANCED MINI-ACE/-ACE SERIES SPECIFICATIONS (CONT.) PARAMETER LOGIC (CONT) CI (Input Capacitance) CIO (Bi-directional signal input capacitance) POWER SUPPLY REQUIREMENTS Voltages/Tolerances * +5V (RAM for 61860/4/5), Logic for BU-61XX5) (Note 12) * +3.3V (Logic for BU-61XX0/3/4) (Note 12) * +5V (Ch. A, Ch. B) Current Drain (Total Hybrid) * BU-61865XX-XX0 +5V (Logic, RAM, Ch. A, Ch. B) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle * BU-61865/0X3-XX2 +5V (Logic, RAM, Ch. A, Ch. B) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle * BU-61864XX-XX0 +5V (RAM, Ch. A, Ch. B) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle * 3.3V Logic * BU-61864/0X3-XX2 +5V (RAM, Ch. A, Ch. B) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle * 3.3V Logic * BU-61745XX-XX0. BU-61845XX-XX0 +5V (Logic, RAM, Ch. A, Ch. B) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle * BU-61745/0X3-XX2, BU-61845/0X3-XX2 +5V (Logic, RAM, Ch. A, Ch. B) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle * BU-61743XX-XX0, BU-61843XX-XX0 +5V (Ch. A, Ch. B) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle * 3.3V Logic * BU-61743/0X3-XX2, BU-61843/0X3-XX2 +5V (Ch. A, Ch. B) * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle * 3.3V Logic MIN TYP 50 50 MAX UNITS pF pF -0.3 -0.3 -0.3 -0.3 -0.3 6.0 6.0 7.0 6.0 6.0 V V V V V 4.5 3.0 4.75 5.0 3.3 5.0 5.5 3.6 5.25 V V V 2.5 5 0.200 0.860 10 k pF Vp-p Vpeak 116 217 318 519 180 285 390 600 mA mA mA mA 6 7 9 Vp-p 116 228 340 563 180 296 412 645 mA mA mA mA 18 20 -250 20 22 27 27 10 250 Vp-p Vp-p mVp-p mVp 100 200 150 250 300 300 nsec nsec 66 163 260 454 25 120 225 330 540 40 mA mA mA mA mA 2.1 0.8*Vcc 0.7 0.2*Vcc 0.4 1.0 V V V V V V 66 174 282 498 25 120 236 352 585 40 mA mA mA mA mA 116 222 328 540 160 265 370 580 mA mA mA mA -10 -350 -10 -350 -350 -350 -10 -10 2.4 2.4 10 -50 10 -33 -50 -33 10 10 A A A A A A A A V V 116 233 350 584 160 276 392 625 mA mA mA mA 0.4 0.4 3.4 -3.4 2.2 -2.2 V V mA mA mA mA 65 169 273 481 25 100 205 310 520 40 mA mA mA mA mA 65 180 295 525 25 100 216 332 565 40 mA mA mA mA mA Data Device Corporation www.ddc-web.com 3 BU-6174X/6184X/6186X M-12/04-0 TABLE 1. ENHANCED MINI-ACE/-ACE SERIES SPECIFICATIONS (CONT.) PARAMETER POWER DISSIPATION (NOTE 14) Total Hybrid * BU-61865XX-XX0 * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle * BU-61865/0X3-XX2 * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle * BU-61864XX-XX0 * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle * BU-61864/0X3-XX2 * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle * BU-61745XX-XX0, BU-61845XX-XX0 * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle * BU-61745/0X3-XX2, BU-61845/0X3-XX2 * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle * BU-61743XX-XX0, BU-61843XX-XX0 * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle * BU-61743/0X3-XX2, BU-61843/0X3-XX2 * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle Hottest Die * BU-61XXXXX-XX0 * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle * BU-61XXXX3-XX2 * Idle * 25% Transmitter Duty Cycle * 50% Transmitter Duty Cycle * 100% Transmitter Duty Cycle CLOCK INPUT Frequency * Nominal Value * Default Mode * Option * Option * Option * Long Term Tolerance * 1553A Compliance * 1553B Compliance MIN TYP MAX UNITS TABLE 1. ENHANCED MINI-ACE/-ACE SERIES SPECIFICATIONS (CONT.) PARAMETER CLOCK INPUT (CONT) * Short Term Tolerance, 1 second * 1553A Compliance * 1553B Compliance * Duty Cycle 1553 MESSAGE TIMING Completion of CPU Write (BC Start)-to-Start of First Message (for Non-enhanced BC Mode) BC Intermessage Gap (Note 8) Non-enhanced (Mini-ACE compatible) BC mode Enhanced BC mode (Note 9) MIN TYP MAX UNITS 0.64 0.93 1.22 1.80 0.64 0.99 1.33 2.03 0.44 0.75 1.05 1.66 0.44 0.80 1.17 1.89 0.64 0.93 1.22 1.81 0.99 1.22 1.45 1.90 0.99 1.28 1.58 2.16 0.80 1.03 1.26 1.71 0.80 1.09 1.39 1.97 0.88 1.11 1.33 1.97 W W W W W W W W W W W W W W W W W W W W -0.001 -0.01 40 2.5 0.001 0.01 60 % % % s 9.5 10.0 to 10.5 17.5 21.5 49.5 127 4 18.0 22.5 50.5 129.5 19.5 23.5 51.5 131 7 s s s s s s s s BC/RT/MT Response Timeout (Note 10) * 18.5 nominal * 22.5 nominal * 50.5 nominal * 128.0 nominal RT Response Time (mid-parity to mid-sync) (Note 11) Transmitter Watchdog Timeout THERMAL Operating Case/Ball Temperature -1XX, -4XX -2XX, -5XX -3XX, -8XX Operating Junction Temperature Storage Temperature Lead Temperature (soldering, 10 sec.) Thermal Resistance Enhanced Mini-ACE Ceramic Flat pack / Gull Wing package Junction-to-Case, Hottest Die (JC) -ACE BGA package (see Thermal Management Section) Junction-to-Balls, Hottest Die (JB) PHYSICAL CHARACTERISTICS Size Enhanced Mini-ACE Ceramic Flat pack / Gull Wing package -ACE BGA package -ACE Moisture Sensitivity Level Weight Enhanced Mini-ACE Ceramic Flat pack / Gull Wing package -ACE BGA package 660.5 0.64 0.99 1.34 2.04 0.41 0.70 0.94 1.40 0.88 1.17 1.46 2.05 0.63 0.85 1.07 1.51 W W W W W W W W -55 -40 0 -55 -65 +125 +85 +70 150 150 +300 C C C C C C C 9 11 C/W 0.41 0.72 0.97 1.45 0.63 0.86 1.09 1.56 W W W W 18 22 C/W 0.18 0.42 0.66 1.14 0.18 0.48 0.78 1.39 0.28 0.51 0.75 1.22 0.28 0.58 0.88 1.48 W W W W W W W W 1.0 X 1.0 X 0.155 (25.4 x 25.4 x 3.94) 0.815 X 0.815 X 0.120 (20.7 x 20.7 x 3.05) MSL-3 in. (mm) in. (mm) 0.6 (17) .088 (2.5) oz (g) oz (g) 16.0 12.0 10.0 20.0 -0.01 -0.10 0.01 0.10 MHz MHz MHz MHz % % TABLE 1 NOTES: Notes 1 through 6 are applicable to the Receiver Differential Resistance and Differential Capacitance specifications: (1) Specifications include both transmitter and receiver (tied together internally). Data Device Corporation www.ddc-web.com 4 BU-6174X/6184X/6186X M-12/04-0 (2) Impedance parameters are specified directly between pins TX/RX_A(B) and TX/RX_A(B) of the Enhanced Mini-ACE/-ACE hybrid. It is assumed that all power and ground inputs to the hybrid are connected. The specifications are applicable for both unpowered and powered conditions. The specifications assume a 2 volt rms balanced, differential, sinusoidal input. The applicable frequency range is 75 kHz to 1 MHz. Minimum resistance and maximum capacitance parameters are guaranteed over the operating range, but are not tested. Assumes a common mode voltage within the frequency range of dc to 2 MHz, applied to pins of the isolation transformer on the stub side (either direct or transformer coupled), and referenced to hybrid ground. Transformer must be a DDC recommended transformer or other transformer that provides an equivalent minimum CMRR. Typical value for minimum intermessage gap time. Under software control, this may be lengthened (to 65,535 ms - message time) in increments of 1 s. If ENHANCED CPU ACCESS, bit 14 of Configuration Register #6, is set to logic "1", then host accesses during BC Start-of-Message (SOM) and End-of-Message (EOM) transfer sequences could have the effect of lengthening the intermessage gap time. For each host access during an SOM or EOM sequence, the intermessage gap time will be lengthened by 6 clock cycles. Since there are 7 internal transfers during SOM and 5 during EOM, this could theoretically lengthen the intermessage gap by up to 72 clock cycles; i.e., up to 7.2 ms with a 10 MHz clock, 6.0 s with a 12 MHz clock, 4.5 s with a 16 MHz clock, or 3.6 s with a 20 MHz clock. For Enhanced BC mode, the typical value for intermessage gap time is approximately 10 clock cycles longer than for the nonenhanced BC mode. That is, an addition of 1.0 s at 10 MHz, 833 ns at 12 MHz, 625 ns at 16 MHz, or 500 ns at 20 MHz. Software programmable (4 options). Includes RT-to-RT Timeout (measured mid-parity of transmit Command Word to mid-sync of transmitting RT Status Word). Measured from mid-parity crossing of Command Word to mid-sync crossing of RT's Status Word. External 10 F tantalum and 0.1 F capacitors should be located as close as possible to input signals "+5V Vcc CH A" and "+5V Vcc CH B", and a 0.1 F to input signal "+5V/+3.3V Logic". For the BU61864 and BU-61865, and BU-61860 versions, there should also be a 0.1 F capacitor for the input signal "+5V RAM". MIL-STD-1760 requires a 20 Vp-p minimum output on the stub connection. Power dissipation specifications assume a transformer coupled configuration with external dissipation (while transmitting) of: 0.14 watts for the active isolation transformer, 0.08 watts for the active bus coupling transformer, 0.45 watts for each of the two bus isolation resistors and 0.15 watts for each of the two bus termination resistors. INTRODUCTION The BU-61740/61743/61745 RT, and BU-61840/61843/61845/ 61860/61864/61865 BC/RT/MT Enhanced Mini-ACE/-ACE family of MIL-STD-1553 terminals comprise a complete integrated interface between a host processor and a MIL-STD-1553 bus. The Enhanced Mini-ACE is available as a 1.0 square inch flat pack or gull wing package. The -ACE is available as a 0.815 square inch BGA package. These terminals are nearly 100% software compatible with the previous generation Mini-ACE and Mini-ACE Plus terminals, and are software compatible with the original ACE series. The Enhanced Mini-ACE provides complete multiprotocol support of MIL-STD-1553A/B/McAir and STANAG 3838. All versions integrate a dual transceiver, along with protocol, host interface, memory management logic, and either 4K or 64K words of RAM. In addition, the BU-61864 and BU-61865 BC/RT/MT terminals include 64K words of internal RAM, with built-in parity checking. The Enhanced Mini-ACE includes a 5V voltage source transceiver for improved line driving capability, with options for MIL-STD1760 and McAir compatibility, and the -ACE is MIL-STD-1760 compatible. As a means of reducing power consumption, there are versions for which the logic is powered by 3.3V, rather than 5V. To provide further flexibility, the Enhanced Mini-ACE/-ACE may operate with a choice of 10, 12, 16, or 20 MHz clock inputs. One of the new salient features of the Enhanced Mini-ACE/-ACE is its Enhanced bus controller architecture. The Enhanced BC's highly autonomous message sequence control engine provides a means for offloading the host processor for implementing multiframe message scheduling, message retry schemes, data double buffering, and asynchronous message insertion. For the purpose of performing messaging to the host processor, the Enhanced BC mode includes a General Purpose Queue, along with user-defined interrupts. A second major new feature of the Enhanced Mini-ACE/-ACE is the incorporation of a fully autonomous built-in self-test. This test provides comprehensive testing of the internal protocol logic. A separate test verifies the operation of the internal RAM. Since the self-tests are fully autonomous, they eliminate the need for the host to write and read stimulus and response vectors. The Enhanced Mini-ACE/-ACE RT offers the same choices of single, double, and circular buffering for individual subaddresses as ACE and Mini-ACE (Plus). New enhancements to the RT architecture include a global circular buffering option for multiple (or all) receive subaddresses, a 50% rollover interrupt for circular buffers, an interrupt status queue for logging up to 32 interrupt events, and an option to automatically initialize to RT mode with the Busy bit set. The interrupt status queue and 50% rollover interrupt features are also included as improvements to the Enhanced Mini-ACE/-ACE's Monitor architecture. BU-6174X/6184X/6186X M-12/04-0 (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) Data Device Corporation www.ddc-web.com 5 To minimize board space and "glue" logic, the Enhanced MiniACE/-ACE terminals provide the same wide choice of host interface configurations as the ACE and Mini-ACE (Plus). This includes support of interfaces to 16-bit or 8-bit processors, memory or port type interfaces, and multiplexed or non-multiplexed address/data buses. In addition, with respect to ACE/Mini-ACE (Plus), the worst case processor wait time has been significantly reduced. For example, assuming a 16 MHz clock, this time has been reduced from 2.8 s to 632 ns for read accesses, and to 570 ns for write accesses. The Enhanced Mini-ACE series terminals operate over the full military temperature range of -55 to +125C. Available screened to MIL-PRF-38534C, the terminals are ideal for military and industrial processor-to-1553 applications. TABLE 2. ADDRESS MAPPING ADDRESS LINES A4 A3 A2 A1 A0 REGISTER DESCRIPTION/ACCESSIBILITY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 Interrupt Mask Register #1 (RD/WR) Configuration Register #1 (RD/WR) Configuration Register #2 (RD/WR) Start/Reset Register (WR) Non-Enhanced BC/RT Command Stack Pointer / Enhanced BC Instruction List Pointer Register (RD) BC Control Word / RT Subaddress Control Word Register (RD/WR) Time Tag Register (RD/WR) Interrupt Status Register #1 (RD) Configuration Register #3 (RD/WR) Configuration Register #4 (RD/WR) Configuration Register #5 (RD/WR) RT / Monitor Data Stack Address Register (RD) BC Frame Time Remaining Register (RD) BC Time Remaining to Next Message Register (RD) Non-Enhanced BC Frame Time / Enhanced BC Initial Instruction Pointer / RT Last Command / MT Trigger Word Register(RD/WR) RT Status Word Register (RD) RT BIT Word Register (RD) Test Mode Register 0 Test Mode Register 1 Test Mode Register 2 Test Mode Register 3 Test Mode Register 4 Test Mode Register 5 Test Mode Register 6 Test Mode Register 7 Configuration Register #6 (RD/WR) Configuration Register #7 (RD/WR) RESERVED BC Condition Code Register (RD) BC General Purpose Flag Register (WR) BIT Test Status Register (RD) Interrupt Mask Register #2 (RD/WR) Interrupt Status Register #2 (RD) BC General Purpose Queue Pointer / RT-MT Interrupt Status Queue Pointer Register (RD/WR) 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 TEST COMPONENTS Daisy chain mechanical samples of the -ACE, 128-ball BGA (BU-61863B3-601) are available. These are used to verify both the electrical and mechanical integrity of the solder joints between the BGA package and the board. Ball pairs are internally wired so that the user can test for electrical continuity between balls. Refer to TABLE 57 for connection details. Although these units are inert, they are fully populated with silicon die so that they closely match the thermal and mechanical characteristics of standard production units. Internal daisy chain interconnections are made by copper PWB traces. 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 BU-61860E3 MICRO-ACE (+5.0V) & TRANSFORMER EVALUATION BOARD The BU-61860E3 board is intended to support customers who are interested in electrically connecting and evaluating the performance of +5.0V Enhanced Mini-ACE and/or +5.0V Micro-ACE series of products. The user will be able to quickly perform functional tests and run their system software utilizing this relatively small (2.0" x 2.5") evaluation board. As shown in FIGURE 2, the BU-61860E3 consists of a PC board incorporating a +5.0V Micro-ACE (BU-61860B3, BC/RT/MT with 64K x 17 RAM), necessary decoupling capacitors, and associated isolation transformers. The MIL-STD-1760 outputs are user configurable as either Stub (transformer) or Direct Coupling. The board supports the signal fan-out of the +5.0V Micro-ACE to 112 pins subdivided into (4) dual inline, berg type pin rows. These pins (0.025" square max) and their row placement adhere to standard 0.100" vector board spacing. 1 1 1 1 1 1 1 1 TRANSCEIVERS The transceivers in the Enhanced Mini-ACE/-ACE series terminals are fully monolithic, requiring only a +5 volt power input. The transmitters are voltage sources, which provide improved line driving capability over current sources. This serves to improve performance on long buses with many taps. The transmitters also offer an option which satisfies the MIL-STD-1760 Data Device Corporation www.ddc-web.com 1 1 6 BU-6174X/6184X/6186X M-12/04-0 requirement for a minimum of 20 volts peak-to-peak, transformer coupled output. Besides eliminating the demand for an additional power supply, the use of a +5V only transceiver requires the use of a step-up, rather than a step-down, isolation transformer. This provides the advantage of a higher terminal input impedance than is possible for a 15 volt or 12 volt transmitter. As a result, there is a greater margin for the input impedance test, mandated for the 1553 validation test. This allows for longer cable lengths between a system connector and the isolation transformers of an embedded 1553 terminal. To provide compatibility to McAir specs, the Enhanced MiniACE's are available with an option for transmitters with increased rise and fall times. Additionally, for MIL-STD-1760 applications, the Enhanced MiniACE provides an option for a minimum stub voltage level of 20 volts peak-to-peak, transformer coupled. The receiver sections of the Enhanced Mini-ACE/-ACE are fully compliant with MIL-STD-1553B Notice 2 in terms of front end overvoltage protection, threshold, common mode rejection, and word error rate. REGISTER AND MEMORY ADDRESSING The software interface of the Enhanced Mini-ACE/-ACE to the host processor consists of 24 internal operational registers for normal operation, an additional 24 test registers, plus 64K words of shared memory address space. The Enhanced Mini-ACE/-ACE's 4K X 16 or 64K X 17 internal RAM resides in this address space. For normal operation, the host processor only needs to access the lower 32 register address locations (00-1F). The next 32 locations (20-3F) should be reserved, since many of these are used for factory test. INTERNAL REGISTERS The address mapping for the Enhanced Mini-ACE/-ACE registers is illustrated in TABLE 2. 0.062 (1.57) 4X 0.230 [5.84] 23 21 19 17 15 13 11 9 7 5 3 1 P4 P3 P1 32 30 28 26 31 29 27 25 24 22 20 18 16 14 12 10 8 6 4 2 32 30 28 26 31 29 27 25 24 22 23 21 24 22 23 21 20 18 19 17 20 18 19 17 2.200 [55.88] 2X 15 EQUAL SP @ 0.100 [2.54]= 1.500 [38.10] (TOL-NONCUM) 2.300 [58.42] U2 U2 16 15 16 15 14 13 14 13 112 X 0.025 .001 [0.64] 12 10 11 9 12 10 11 9 8 6 7 5 8 6 7 5 0.350 [8.89] (MAX) 2.515 [63.88] (MAX) 4 2 3 1 4 2 3 1 T2 T1 2X 0.600 [15.24] 0.100 [2.54] 23 21 19 17 15 13 11 9 7 5 3 1 S/N DC P2 24 22 20 18 16 14 12 10 8 6 4 2 0.350 [8.89] (MAX) 0.100 [2.54] 0.100 [2.54] 0.150 [3.81] 2 X 0.300 [7.62] 2 X 11 EQUAL SPACES @ 0.100 [2.54] = 1.100 [27.94] (TOL NON-CUM) 1.600 [40.64] 1.700 [43.18] 2.015 [51.18] (MAX) FIGURE 2. TRANSFORMER EVALUATION BOARD Data Device Corporation www.ddc-web.com 7 BU-6174X/6184X/6186X M-12/04-0 TABLE 3. INTERRUPT MASK REGISTER #1 (READ/WRITE 00H) BIT 15(MSB) RESERVED 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB) RAM PARITY ERROR BC/RT TRANSMITTER TIMEOUT BC/RT COMMAND STACK ROLLOVER MT COMMAND STACK ROLLOVER MT DATA STACK ROLLOVER HANDSHAKE FAIL BC RETRY RT ADDRESS PARITY ERROR TIME TAG ROLLOVER RT CIRCULAR BUFFER ROLLOVER BC CONTROL WORD/RT SUBADDRESS CONTROL WORD EOM BC END OF FRAME FORMAT ERROR BC STATUS SET/RT MODE CODE/MT PATTERN TRIGGER END OF MESSAGE DESCRIPTION TABLE 4. CONFIGURATION REGISTER #1 (READ/WRITE 01H) BIT BC FUNCTION (Bits 11-0 Enhanced Mode Only) RT WITHOUT ALTERNATE STATUS (logic 1) (logic 0) CURRENT AREA B/A RT WITH ALTERNATE STATUS (Enhanced Only) (logic 1) (logic 0) CURRENT AREA B/A MONITOR FUNCTION (Enhanced mode only bits 12-0) (logic 0) (logic 1) CURRENT AREA B/A MESSAGE MONITOR ENABLED TRIGGER WORD ENABLED START-ON-TRIGGER STOP-ON-TRIGGER NOT USED EXTERNAL TRIGGER ENABLED NOT USED NOT USED NOT USED NOT USED MONITOR ENABLED(Read Only) MONITOR TRIGGERED (Read Only) MONITOR ACTIVE (Read Only) 15 (MSB) RT/BC-MT (logic 0) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (LSB) MT/BC-RT (logic 0) CURRENT AREA B/A MESSAGE STOP-ON-ERROR FRAME STOP-ON-ERROR STATUS SET STOP-ON-MESSAGE STATUS SET STOP-ON-FRAME FRAME AUTO-REPEAT MESSAGE MONITOR ENABLED MESSAGE MONITOR (MMT) ENABLED DYNAMIC BUS CONTROL ACCEPTANCE BUSY SERVICE REQUEST SSFLAG S10 S09 S08 S07 S06 S05 S04 S03 S02 S01 S00 EXTERNAL TRIGGER ENABLED RTFLAG (Enhanced Mode Only) INTERNAL TRIGGER ENABLED INTERMESSAGE GAP TIMER ENABLED RETRY ENABLED DOUBLED/SINGLE RETRY BC ENABLED (Read Only) BC FRAME IN PROGRESS (Read Only) BC MESSAGE IN PROGRESS (Read Only) NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED RT MESSAGE IN PROGRESS RT MESSAGE IN (Enhanced mode only,Read Only) PROGRESS (Read Only) Data Device Corporation www.ddc-web.com 8 BU-6174X/6184X/6186X M-12/04-0 TABLE 5. CONFIGURATION REGISTER #2 (READ/WRITE 02H) BIT DESCRIPTION BIT 15(MSB) ENHANCED INTERRUPTS 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB) RAM PARITY ENABLE BUSY LOOKUP TABLE ENABLE RX SA DOUBLE BUFFER ENABLE OVERWRITE INVALID DATA 256-WORD BOUNDARY DISABLE TIME TAG RESOLUTION 2 TIME TAG RESOLUTION 1 TIME TAG RESOLUTION 0 CLEAR TIME TAG ON SYNCHRONIZE LOAD TIME TAG ON SYNCHRONIZE INTERRUPT STATUS AUTO CLEAR LEVEL/PULSE INTERRUPT REQUEST CLEAR SERVICE REQUEST ENHANCED RT MEMORY MANAGEMENT SEPARATE BROADCAST DATA TABLE 8. BC CONTROL WORD REGISTER (READ/WRITE 04H) DESCRIPTION TRANSMIT TIME TAG FOR SYNCHRONIZE MODE COM15(MSB) MAND 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB) MESSAGE ERROR MASK SERVICE REQUEST BIT MASK BUSY BIT MASK SUBSYSTEM FLAG BIT MASK TERMINAL FLAG BIT MASK RESERVED BITS MASK RETRY ENABLED BUS CHANNEL A/B OFF-LINE SELF-TEST MASK BROADCAST BIT EOM INTERRUPT ENABLE 1553A/B SELECT MODE CODE FORMAT BROADCAST FORMAT RT-to-RT FORMAT TABLE 6. START/RESET REGISTER (WRITE 03H) BIT 15(MSB) RESERVED 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB) RESERVED RESERVED RESERVED CLEAR RT HALT CLEAR SELF-TEST REGISTER INITIATE RAM SELF-TEST RESERVED INITIATE PROTOCOL SELF-TEST BC/MT STOP-ON-MESSAGE BC STOP-ON-FRAME TIME TAG TEST CLOCK TIME TAG RESET INTERRUPT RESET BC/MT START RESET DESCRIPTION TABLE 9. RT SUBADDRESS CONTROL WORD (READ/WRITE 04H) BIT 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB) TX: EOM INT TX: CIRC BUF INT TX: MEMORY MANAGEMENT 2 (MM2) TX: MEMORY MANAGEMENT 1 (MM1) TX: MEMORY MANAGEMENT 0 (MM0) RX: EOM INT RX: CIRC BUF INT RX: MEMORY MANAGEMENT 2 (MM2) RX: MEMORY MANAGEMENT 1 (MM1) RX: MEMORY MANAGEMENT 0 (MM0) BCST: EOM INT BCST: CIRC BUF INT BCST: MEMORY MANAGEMENT 2 (MM2) BCST: MEMORY MANAGEMENT 1 (MM1) BCST: MEMORY MANAGEMENT 0 (MM0) DESCRIPTION 15(MSB) RX: DOUBLE BUFFER ENABLE TABLE 7. BC/RT COMMAND STACK POINTER REG. (READ 03H) BIT * * * 0(LSB) * * * COMMAND STACK POINTER 0 DESCRIPTION BIT 15(MSB) COMMAND STACK POINTER 15 TABLE 10. TIME TAG REGISTER (READ/WRITE 05H) DESCRIPTION * * * TIME TAG 0 15(MSB) TIME TAG 15 * * * 0(LSB) Data Device Corporation www.ddc-web.com 9 BU-6174X/6184X/6186X M-12/04-0 TABLE 11. INTERRUPT STATUS REGISTER #1 (READ 06H) BIT DESCRIPTION 15(MSB) MASTER INTERRUPT 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB) RAM PARITY ERROR TRANSMITTER TIMEOUT BC/RT COMMAND STACK ROLLOVER MT COMMAND STACK ROLLOVER MT DATA STACK ROLLOVER HANDSHAKE FAIL BC RETRY RT ADDRESS PARITY ERROR TIME TAG ROLLOVER RT CIRCULAR BUFFER ROLLOVER BC CONTROL WORD/RT SUBADDRESS CONTROL WORD EOM BC END OF FRAME FORMAT ERROR BC STATUS SET / RT MODE CODE / MT PATTERN TRIGGER END OF MESSAGE TABLE 13. CONFIGURATION REGISTER #4 (READ/WRITE 08H) BIT DESCRIPTION 15(MSB) EXTERNAL BIT WORD ENABLE 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB) INHIBIT BIT WORD IF BUSY MODE COMMAND OVERRIDE BUSY EXPANDED BC CONTROL WORD ENABLE BROADCAST MASK ENA/XOR RETRY IF -A AND M.E. RETRY IF STATUS SET 1ST RETRY ALT/SAME BUS 2ND RETRY ALT/SAME BUS VALID M.E./NO DATA VALID BUSY/NO DATA MT TAG GAP OPTION LATCH RT ADDRESS WITH CONFIG #5 TEST MODE 2 TEST MODE 1 TEST MODE 0 TABLE 12. CONFIGURATION REGISTER #3 (READ/WRITE 07H) BIT DESCRIPTION 15(MSB) ENHANCED MODE ENABLE 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB) BC/RT COMMAND STACK SIZE 1 BC/RT COMMAND STACK SIZE 0 MT COMMAND STACK SIZE 1 MT COMMAND STACK SIZE 0 MT DATA STACK SIZE 2 MT DATA STACK SIZE 1 MT DATA STACK SIZE 0 ILLEGALIZATION DISABLED OVERRIDE MODE T/R ERROR ALTERNATE STATUS WORD ENABLE ILLEGAL RX TRANSFER DISABLE BUSY RX TRANSFER DISABLE RTFAIL / RTFLAG WRAP ENABLE 1553A MODE CODES ENABLE ENHANCED MODE CODE HANDLING TABLE 14. CONFIGURATION REGISTER #5 (READ/WRITE 09H) BIT DESCRIPTION 15(MSB) 12 / 16 MHZ CLOCK SELECT 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB) SINGLE-ENDED SELECT EXTERNAL TX INHIBIT A EXTERNAL TX INHIBIT B EXPANDED CROSSING ENABLED RESPONSE TIMEOUT SELECT 1 RESPONSE TIMEOUT SELECT 0 GAP CHECK ENABLED BROADCAST DISABLED RT ADDRESS LATCH/TRANSPARENT RT ADDRESS 4 RT ADDRESS 3 RT ADDRESS 2 RT ADDRESS 1 RT ADDRESS 0 RT ADDRESS PARITY TABLE 15. RT / MONITOR DATA STACK ADDRESS REGISTER (READ/WRITE 0AH) BIT * * * 0(LSB) * * * RT / MONITOR DATA STACK ADDRESS 0 DESCRIPTION 15(MSB) RT / MONITOR DATA STACK ADDRESS 15 Data Device Corporation www.ddc-web.com 10 BU-6174X/6184X/6186X M-12/04-0 TABLE 16. BC FRAME TIME REMAINING REGISTER (READ/WRITE 0BH) BIT DESCRIPTION BIT 15(MSB) BC FRAME TIME REMAINING 15 * * * 0(LSB) * * * BC FRAME TIME REMAINING 0 TABLE 20. RT BIT WORD REGISTER (READ 0FH) DESCRIPTION 15(MSB) TRANSMITTER TIMEOUT 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB) LOOP TEST FAILURE B LOOP TEST FAILURE A HANDSHAKE FAILURE TRANSMITTER SHUTDOWN B TRANSMITTER SHUTDOWN A TERMINAL FLAG INHIBITED BIT TEST FAIL HIGH WORD COUNT LOW WORD COUNT INCORRECT SYNC RECEIVED PARITY / MANCHESTER ERROR RECEIVED RT-to-RT GAP / SYNCH / ADDRESS ERROR RT-to-RT NO RESPONSE ERROR RT-to-RT 2ND COMMAND WORD ERROR COMMAND WORD CONTENTS ERROR Note: resolution = 100 s per LSB TABLE 17. BC MESSAGE TIME REMAINING REGISTER (READ/WRITE 0CH) BIT DESCRIPTION 15(MSB) BC MESSAGE TIME REMAINING 15 * * * 0(LSB) * * * BC MESSAGE TIME REMAINING 0 Note: resolution = 1 s per LSB TABLE 18. BC FRAME TIME / RT LAST COMMAND / MT TRIGGER REGISTER (READ/WRITE 0DH) BIT 15(MSB) BIT 15 * * * 0(LSB) * * * BIT 0 DESCRIPTION TABLE 21. CONFIGURATION REGISTER #6 (READ/WRITE 18H) BIT DESCRIPTION 15(MSB) ENHANCED BUS CONTROLLER 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB) ENHANCED CPU ACCESS COMMAND STACK POINTER INCREMENT ON EOM (RT, MT) GLOBAL CIRCULAR BUFFER ENABLE GLOBAL CIRCULAR BUFFER SIZE 2 GLOBAL CIRCULAR BUFFER SIZE 1 GLOBAL CIRCULAR BUFFER SIZE 0 DISABLE INVALID MESSAGES TO INTERRUPT STATUS QUEUE DISABLE VALID MESSAGES TO INTERRUPT STATUS QUEUE INTERRUPT STATUS QUEUE ENABLE RT ADDRESS SOURCE ENHANCED MESSAGE MONITOR RESERVED 64-WORD REGISTER SPACE CLOCK SELECT 1 CLOCK SELECT 0 TABLE 19. RT STATUS WORD REGISTER (READ/WRITE 0EH) BIT 15(MSB) LOGIC "0" 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB) LOGIC "0" LOGIC "0" LOGIC "0" LOGIC "0" MESSAGE ERROR INSTRUMENTATION SERVICE REQUEST RESERVED RESERVED RESERVED BROADCAST COMMAND RECEIVED BUSY SSFLAG DYNAMIC BUS CONTROL ACCEPT TERMINAL FLAG DESCRIPTION Data Device Corporation www.ddc-web.com 11 BU-6174X/6184X/6186X M-12/04-0 TABLE 22. CONFIGURATION REGISTER #7 (READ/WRITE 19H) BIT DESCRIPTION 15(MSB) MEMORY MANAGEMENT BASE ADDRESS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB) MEMORY MANAGEMENT BASE ADDRESS 14 MEMORY MANAGEMENT BASE ADDRESS 13 MEMORY MANAGEMENT BASE ADDRESS 12 MEMORY MANAGEMENT BASE ADDRESS 11 MEMORY MANAGEMENT BASE ADDRESS 10 RESERVED RESERVED RESERVED RESERVED RESERVED RT HALT ENABLE 1553B RESPONSE TIME ENHANCED TIMETAG SYNCHRONIZE ENHANCED BC WATCHDOG TIMER ENABLED MODE CODE RESET / INCMD SELECT TABLE 24. BC GENERAL PURPOSE FLAG REGISTER (WRITE 1BH) BIT DESCRIPTION 15(MSB) CLEAR GENERAL PURPOSE FLAG 7 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB) CLEAR GENERAL PURPOSE FLAG 6 CLEAR GENERAL PURPOSE FLAG 5 CLEAR GENERAL PURPOSE FLAG 4 CLEAR GENERAL PURPOSE FLAG 3 CLEAR GENERAL PURPOSE FLAG 2 CLEAR GENERAL PURPOSE FLAG 1 CLEAR GENERAL PURPOSE FLAG 0 SET GENERAL PURPOSE FLAG 7 SET GENERAL PURPOSE FLAG 6 SET GENERAL PURPOSE FLAG 5 SET GENERAL PURPOSE FLAG 4 SET GENERAL PURPOSE FLAG 3 SET GENERAL PURPOSE FLAG 2 SET GENERAL PURPOSE FLAG 1 SET GENERAL PURPOSE FLAG 0 TABLE 23. BC CONDITION REGISTER (READ 1BH) BIT 15(MSB) LOGIC "1" 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB) RETRY 1 RETRY 0 BAD MESSAGE MESSAGE STATUS SET GOOD BLOCK TRANSFER FORMAT ERROR NO RESPONSE GENERAL PURPOSE FLAG 7 GENERAL PURPOSE FLAG 6 GENERAL PURPOSE FLAG 5 GENERAL PURPOSE FLAG 4 GENERAL PURPOSE FLAG 3 GENERAL PURPOSE FLAG 2 EQUAL FLAG / GENERAL PURPOSE FLAG 1 LESS THAN FLAG / GENERAL PURPOSE FLAG 1 DESCRIPTION TABLE 25. BIT TEST STATUS FLAG REGISTER (READ 1CH) BIT DESCRIPTION 15(MSB) PROTOCOL BUILT-IN TEST COMPLETE 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB) PROTOCOL BUILT-IN TEST IN-PROGRESS PROTOCOL BUILT-IN TEST PASSED PROTOCOL BUILT-IN TEST ABORT PROTOCOL BUILT-IN-TEST COMPLETE / IN-PROGRESS LOGIC "0" LOGIC "0" LOGIC "0" RAM BUILT-IN TEST COMPLETE RAM BUILT-IN TEST IN-PROGRESS RAM BUILT-IN TEST IN-PASSED LOGIC "0" LOGIC "0" LOGIC "0" LOGIC "0" LOGIC "0" Note: If the Enhanced Mini-ACE is not online in enhanced BC mode (i.e., processing instructions), the BC condition code register will always return a value of 0000. Data Device Corporation www.ddc-web.com 12 BU-6174X/6184X/6186X M-12/04-0 TABLE 26. INTERRUPT MASK REGISTER #2 (READ/WRITE 1DH) BIT 15(MSB) NOT USED 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB) BC OP CODE PARITY ERROR RT ILLEGAL COMMAND/MESSAGE MT MESSAGE RECEIVED GENERAL PURPOSE QUEUE / INTERRUPT STATUS QUEUE ROLLOVER CALL STACK POINTER REGISTER ERROR BC TRAP OP CODE RT COMMAND STACK 50% ROLLOVER RT CIRCULAR BUFFER 50% ROLLOVER MONITOR COMMAND STACK 50% ROLLOVER MONITOR DATA STACK 50% ROLLOVER ENHANCED BC IRQ3 ENHANCED BC IRQ2 ENHANCED BC IRQ1 ENHANCED BC IRQ0 BIT TEST COMPLETE NOT USED DESCRIPTION TABLE 28. BC GENERAL PURPOSE QUEUE POINTER REGISTER RT, MT INTERRUPT STATUS QUEUE POINTER REGISTER (READ/WRITE1FH) BIT DESCRIPTION 15(MSB) QUEUE POINTER BASE ADDRESS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB) QUEUE POINTER BASE ADDRESS 14 QUEUE POINTER BASE ADDRESS 13 QUEUE POINTER BASE ADDRESS 12 QUEUE POINTER BASE ADDRESS 11 QUEUE POINTER BASE ADDRESS 10 QUEUE POINTER BASE ADDRESS 9 QUEUE POINTER BASE ADDRESS 8 QUEUE POINTER BASE ADDRESS 7 QUEUE POINTER BASE ADDRESS 6 QUEUE POINTER ADDRESS 5 QUEUE POINTER ADDRESS 4 QUEUE POINTER ADDRESS 3 QUEUE POINTER ADDRESS 2 QUEUE POINTER ADDRESS 1 QUEUE POINTER ADDRESS 0 TABLE 27. INTERRUPT STATUS REGISTER #2 (READ 1EH) BIT DESCRIPTION 15(MSB) MASTER INTERRUPT 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB) BC OP CODE PARITY ERROR RT ILLEGAL COMMAND/MESSAGE MT MESSAGE RECEIVED GENERAL PURPOSE QUEUE / INTERRUPT STATUS QUEUE ROLLOVER CALL STACK POINTER REGISTER ERROR BC TRAP OP CODE RT COMMAND STACK 50% ROLLOVER RT CIRCULAR BUFFER 50% ROLLOVER MONITOR COMMAND STACK 50% ROLLOVER MONITOR DATA STACK 50% ROLLOVER ENHANCED BC IRQ3 ENHANCED BC IRQ2 ENHANCED BC IRQ1 ENHANCED BC IRQ0 BIT TEST COMPLETE INTERRUPT CHAIN BIT Data Device Corporation www.ddc-web.com 13 BU-6174X/6184X/6186X M-12/04-0 NOTE: TABLES 29 TO 35 ARE NOT REGISTERS, BUT THEY ARE WORDS STORED IN RAM. TABLE 29. BC MODE BLOCK STATUS WORD BIT 15(MSB) EOM 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB) SOM CHANNEL B/A ERROR FLAG STATUS SET FORMAT ERROR NO RESPONSE TIMEOUT LOOP TEST FAIL MASKED STATUS SET RETRY COUNT 1 RETRY COUNT 0 GOOD DATA BLOCK TRANSFER WRONG STATUS ADDRESS / NO GAP WORD COUNT ERROR INCORRECT SYNC TYPE INVALID WORD DESCRIPTION BIT TABLE 31. 1553 COMMAND WORD DESCRIPTION 15(MSB) REMOTE TERMINAL ADDRESS BIT 4 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB) REMOTE TERMINAL ADDRESS BIT 3 REMOTE TERMINAL ADDRESS BIT 2 REMOTE TERMINAL ADDRESS BIT 1 REMOTE TERMINAL ADDRESS BIT 0 TRANSMIT / RECEIVE SUBADDRESS / MODE BIT 4 SUBADDRESS / MODE BIT 3 SUBADDRESS / MODE BIT 2 SUBADDRESS / MODE BIT 1 SUBADDRESS / MODE BIT 0 DATA WORD COUNT / MODE CODE BIT 4 DATA WORD COUNT / MODE CODE BIT 3 DATA WORD COUNT / MODE CODE BIT 2 DATA WORD COUNT / MODE CODE BIT 1 DATA WORD COUNT / MODE CODE BIT 0 TABLE 30. RT MODE BLOCK STATUS WORD BIT 15(MSB) EOM 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB) SOM CHANNEL B/A ERROR FLAG RT-to-RT FORMAT FORMAT ERROR NO RESPONSE TIMEOUT LOOP TEST FAIL DATA STACK ROLLOVER ILLEGAL COMMAND WORD WORD COUNT ERROR INCORRECT DATA SYNC INVALID WORD RT-to-RT GAP / SYNC / ADDRESS ERROR RT-to-RT 2ND COMMAND ERROR COMMAND WORD CONTENTS ERROR 8 7 6 5 4 3 2 1 DESCRIPTION TABLE 32. WORD MONITOR IDENTIFICATION WORD BIT 15(MSB) GAP TIME (MSB) * * * * * * GAP TIME (LSB) WORD FLAG THIS RT BROADCAST ERROR COMMAND / DATA CHANNEL B/A CONTIGUOUS DATA / GAP MODE_CODE DESCRIPTION 0(LSB) Data Device Corporation www.ddc-web.com 14 BU-6174X/6184X/6186X M-12/04-0 TABLE 33. MESSAGE MONITOR MODE BLOCK STATUS WORD BIT 15(MSB) EOM 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB) SOM CHANNEL B/A ERROR FLAG RT-to-RT TRANSFER FORMAT ERROR NO RESPONSE TIMEOUT GOOD DATA BLOCK TRANSFER DATA STACK ROLLOVER RESERVED WORD COUNT ERROR INCORRECT SYNC INVALID WORD RT-to-RT GAP / SYNC / ADDRESS ERROR RT-to-RT 2ND COMMAND ERROR COMMAND WORD CONTENTS ERROR DESCRIPTION BIT TABLE 35. 1553B STATUS WORD DESCRIPTION 15(MSB) REMOTE TERMINAL ADDRESS BIT 4 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB) REMOTE TERMINAL ADDRESS BIT 3 REMOTE TERMINAL ADDRESS BIT 2 REMOTE TERMINAL ADDRESS BIT 1 REMOTE TERMINAL ADDRESS BIT 0 MESSAGE ERROR INSTRUMENTATION SERVICE REQUEST RESERVED RESERVED RESERVED BROADCAST COMMAND RECEIVED BUSY SSFLAG DYNAMIC BUS CONTROL ACCEPTANCE TERMINAL FLAG TABLE 34. RT/MONITOR INTERRUPT STATUS WORD (FOR INTERRUPT STATUS QUEUE) BIT 15 14 13 12 11 10 9 DEFINITION FOR MESSAGE INTERRUPT EVENT TRANSMITTER TIMEOUT ILLEGAL COMMAND MONITOR DATA STACK 50% ROLLOVER MONITOR DATA STACK ROLLOVER RT CIRCULAR BUFFER 50% ROLLOVER RT CIRCULAR BUFFER ROLLOVER MONITOR COMMAND (DESCRIPTOR) STACK 50% ROLLOVER MONITOR COMMAND (DESCRIPTOR) STACK ROLLOVER RT COMMAND (DESCRIPTOR) STACK 50% ROLLOVER RT COMMAND (DESCRIPTOR) STACK ROLLOVER HANDSHAKE FAIL FORMAT ERROR MODE CODE INTERRUPT SUBADDRESS CONTROL WORD EOM END-OF-MESSAGE (EOM) DEFINITION FOR NON-MESSAGE INTERRUPT EVENT NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED NON-TEST REGISTER FUNCTION SUMMARY A summary of the Enhanced Mini-ACE/-ACE's 24 non-test registers follows. INTERRUPT MASK REGISTERS #1 AND #2 Interrupt Mask Registers #1 and #2 are used to enable and disable interrupt requests for various events and conditions. NOTE: Please see Appendix "F" of the Enhanced Mini-ACE User's Guide for important information applicable only to RT MODE operation, enabling of the interrupt status queue and use of specific non-message interrupts. CONFIGURATION REGISTERS #1 AND #2 NOT USED NOT USED NOT USED NOT USED TIME TAG ROLLOVER RT ADDRESS PARITY ERROR PROTOCOL SELF-TEST COMPLETE RAM PARITY ERROR 8 7 6 5 4 3 2 1 0 Configuration Registers #1 and #2 are used to select the MiniACE Mark3's mode of operation, and for software control of RT Status Word bits, Active Memory Area, BC Stop-On-Error, RT Memory Management mode selection, and control of the Time Tag operation. START/RESET REGISTER The Start/Reset Register is used for "command" type functions such as software reset, BC/MT Start, Interrupt reset, Time Tag Reset, Time Tag Register Test, Initiate protocol self-test, Initiate RAM self-test, Clear self-test register, and Clear RT Halt. The Start/Reset Register also includes provisions for stopping the BC in its auto-repeat mode, either at the end of the current message or at the end of the current BC frame. BU-6174X/6184X/6186X M-12/04-0 "1" FOR MESSAGE INTERRUPT EVENT "0" FOR NON-MESSAGE INTERRUPT EVENT Data Device Corporation www.ddc-web.com 15 BC/RT COMMAND STACK REGISTER The BC/RT Command Stack Register allows the host CPU to determine the pointer location for the current or most recent message. vidual receive (broadcast) subaddresses, and the alternate (fully software programmable) RT Status Word. For MT mode, use of the Enhanced Mode enables the Selective Message Monitor, the combined RT/Selective Monitor modes, and the monitor triggering capability. BC INSTRUCTION LIST POINTER REGISTER The BC Instruction List Pointer Register may be read to determine the current location of the Instruction List Pointer for the Enhanced BC mode. RT/MONITOR DATA STACK ADDRESS REGISTER The RT/Monitor Data Stack Address Register provides a read/writable indication of the last data word stored for RT or Monitor modes. BC CONTROL WORD/RT SUBADDRESS CONTROL WORD REGISTER In BC mode, the BC Control Word/RT Subaddress Control Word Register allows host access to the current word or most recent BC Control Word. The BC Control Word contains bits that select the active bus and message format, enable off-line self-test, masking of Status Word bits, enable retries and interrupts, and specify MIL-STD-1553A or -1553B error handling. In RT mode, this register allows host access to the current or most recent Subaddress Control Word. The Subaddress Control Word is used to select the memory management scheme and enable interrupts for the current message. BC FRAME TIME REMAINING REGISTER The BC Frame Time Remaining Register provides a read-only indication of the time remaining in the current BC frame. In the enhanced BC mode, this timer may be used for minor or major frame control, or as a watchdog timer for the BC message sequence control processor. The resolution of this register is 100 s/LSB. BC TIME REMAINING TO NEXT MESSAGE REGISTER The BC Time Remaining to Next Message Register provides a read-only indication of the time remaining before the start of the next message in a BC frame. In the enhanced BC mode, this timer may also be used for the BC message sequence control processor's Delay (DLY) instruction, or for minor or major frame control. The resolution of this register is 1 s/LSB. TIME TAG REGISTER The Time Tag Register maintains the value of a real-time clock. The resolution of this register is programmable from among 2, 4, 8, 16, 32, and 64 s/LSB. The Start-of-Message (SOM) and End-of-Message (EOM) sequences in BC, RT, and Message Monitor modes cause a write of the current value of the Time Tag Register to the stack area of the RAM. BC FRAME TIME/ RT LAST COMMAND /MT TRIGGER WORD REGISTER In BC mode, this register is used to program the BC frame time, for use in the frame auto-repeat mode. The resolution of this register is 100 s/LS, with a range up to 6.55 seconds. In RT mode, this register stores the current (or most previous) 1553 Command Word processed by the Mini-ACE Mark3 RT. In the Word Monitor mode, this register is used to specify a 16-bit Trigger (Command) Word. The Trigger Word may be used to start or stop the monitor, or to generate interrupts. INTERRUPT STATUS REGISTERS #1 AND #2 Interrupt Status Registers #1 and #2 allow the host processor to determine the cause of an interrupt request by means of one or two read accesses. The interrupt events of the two Interrupt Status Registers are mapped to correspond to the respective bit positions in the two Interrupt Mask Registers. Interrupt Status Register #2 contains an INTERRUPT CHAIN bit, used to indicate an interrupt event from Interrupt Status Register #1. BC INITIAL INSTRUCTION LIST POINTER REGISTER The BC Initial Instruction List Pointer Register enables the host to assign the starting address for the enhanced BC Instruction List. CONFIGURATION REGISTERS #3, #4, AND #5 Configuration Registers #3, #4, and #5 are used to enable many of the Mini-ACE Mark3's advanced features that were implemented by the prior generation products, the ACE and Mini-ACE (Plus). For BC, RT, and MT modes, use of the Enhanced Mode enables the various read-only bits in Configuration Register #1. For BC mode, Enhanced Mode features include the expanded BC Control Word and BC Block Status Word, additional Stop-OnError and Stop-On-Status Set functions, frame auto-repeat, programmable intermessage gap times, automatic retries, expanded Status Word Masking, and the capability to generate interrupts following the completion of any selected message. For RT mode, the Enhanced Mode features include the expanded RT Block Status Word, combined RT/Selective Message Monitor mode, automatic setting of the TERMINAL FLAG Status Word bit following a loop test failure; the double buffering scheme for indiData Device Corporation www.ddc-web.com 16 RT STATUS WORD REGISTER AND BIT WORD REGISTERS The RT Status Word Register and BIT Word Registers provide read-only indications of the RT Status and BIT Words. CONFIGURATION REGISTERS #6 AND #7 Configuration Registers #6 and #7 are used to enable the MiniACE Mark3 features that extend beyond the architecture of the ACE/Mini-ACE (Plus). These include the Enhanced BC mode; RT Global Circular Buffer (including buffer size); the RT/MT Interrupt Status Queue, including valid/invalid message filtering; enabling a software-assigned RT address; clock frequency selection; a base address for the "non-data" portion of Mini-ACE BU-6174X/6184X/6186X M-12/04-0 Mark3 memory; LSB filtering for the Synchronize (with data) time tag operations; and enabling a watchdog timer for the Enhanced BC message sequence control engine. determine the current location of the Interrupt Status Queue pointer, which is incremented by the RT/MT message processor. BUS CONTROLLER (BC) ARCHITECTURE NOTE: Please see Appendix "F" of the Enhanced Mini-ACE User's Guide for important information applicable only to RT MODE operation, enabling of the interrupt status queue and use of specific non-message interrupts. The BC functionality for the Enhanced Mini-ACE/-ACE includes two separate architectures: (1) the older, non-Enhanced Mode, which provides complete compatibility with the previous ACE and Mini-ACE (Plus) generation products; and (2) the newer, Enhanced BC mode. The Enhanced BC mode offers several new powerful architectural features. These include the incorporation of a highly autonomous BC message sequence control engine, which greatly serves to offload the operation of the host CPU. The Enhanced BC's message sequence control engine provides a high degree of flexibility for implementing major and minor frame scheduling; capabilities for inserting asynchronous messages in the middle of a frame; to separate 1553 message data from control/status data for the purpose of implementing double buffering and performing bulk data transfers; for implementing message retry schemes, including the capability for automatic bus channel switchover for failed messages; and for reporting various conditions to the host processor by means of 4 userdefined interrupts and a general purpose queue. In both the non-Enhanced and Enhanced BC modes, the Enhanced Mini-ACE/-ACE BC implements all MIL-STD-1553B message formats. Message format is programmable on a message-by-message basis by means of the BC Control Word and the T/R bit of the Command Word for the respective message. The BC Control Word allows 1553 message format, 1553A/B type RT, bus channel, self-test, and Status Word masking to be specified on an individual message basis. In addition, automatic retries and/or interrupt requests may be enabled or disabled for individual messages. The BC performs all error checking required by MIL-STD-1553B. This includes validation of response time, sync type and sync encoding, Manchester II encoding, parity, bit count, word count, Status Word RT Address field, and various RT-to-RT transfer errors. The Enhanced MiniACE/-ACE BC response timeout value is programmable with choices of 18, 22, 50, and 130 s. The longer response timeout values allow for operation over long buses and/or the use of repeaters. In its non-Enhanced Mode, the Enhanced Mini-ACE/-ACE may be programmed to process BC frames of up to 512 messages with no processor intervention. In the Enhanced BC mode, there is no explicit limit to the number of messages that may be processed in a frame. In both modes, it is possible to program for either single frame or frame auto-repeat operation. In the autorepeat mode, the frame repetition rate may be controlled either internally, using a programmable BC frame timer, or from an external trigger input. BC CONDITION CODE REGISTER The BC Condition Code Register is used to enable the host processor to read the current value of the Enhanced BC Message Sequence Control Engine's condition flags. BC GENERAL PURPOSE FLAG REGISTER The BC General Purpose Flag Register allows the host processor to be able to set, clear, or toggle any of the Enhanced BC Message Sequence Control Engine's General Purpose condition flags. BIT TEST STATUS REGISTER The BIT Test Status Register is used to provide read-only access to the status of the protocol and RAM built-in self-tests (BIT). BC GENERAL PURPOSE QUEUE POINTER The BC General Purpose Queue Pointer provides a means for initializing the pointer for the General Purpose Queue, for the Enhanced BC mode. In addition, this register enables the host to determine the current location of the General Purpose Queue pointer, which is incremented internally by the Enhanced BC message sequence control engine. RT/MT INTERRUPT STATUS QUEUE POINTER The RT/MT Interrupt Status Queue Pointer provides a means for initializing the pointer for the Interrupt Status Queue, for RT, MT, and RT/MT modes. In addition, this register enables the host to BC INSTRUCTION LIST BC INSTRUCTION LIST POINTER REGISTER INITIALITIZE BY REGISTER 0D (RD/WR); READ CURRENT VALUE VIA REGISTER 03 (RD ONLY) MESSAGE CONTROL/STATUS BLOCK OP CODE PARAMETER (POINTER) BC CONTROL WORD COMMAND WORD (Rx Command for RT-to-RT transfer) DATA BLOCK POINTER DATA BLOCK TIME-TO-NEXT MESSAGE TIME TAG WORD BLOCK STATUS WORD LOOPBACK WORD RT STATUS WORD 2nd (Tx) COMMAND WORD (for RT-to-RT transfer) 2nd RT STATUS WORD (for RT-to-RT transfer) FIGURE 3. BC MESSAGE SEQUENCE CONTROL Data Device Corporation www.ddc-web.com BU-6174X/6184X/6186X M-12/04-0 17 ENHANCED BC MODE: MESSAGE SEQUENCE CONTROL One of the major new architectural features of the Enhanced Mini-ACE/-ACE series is its advanced capability for BC message sequence control. The Enhanced Mini-ACE/-ACE supports highly autonomous BC operation, which greatly offloads the operation of the host processor. The operation of the Enhanced Mini-ACE/-ACE's message sequence control engine is illustrated in FIGURE 3. The BC message sequence control involves an instruction list pointer register; an instruction list which contains multiple 2-word entries; a message control/status stack, which contains multiple 8-word or 10word descriptors; and data blocks for individual messages. The initial value of the instruction list pointer register is initialized by the host processor (via Register 0D), and is incremented by the BC message sequence processor (host readable via Register 03). During operation, the message sequence control processor fetches the operation referenced by the instruction list pointer register from the instruction list. Note that the pointer parameter referencing the first word of a message's control/status block (the BC Control Word) must contain an address value that is modulo 8. Also, note that if the message is an RT-to-RT transfer, the pointer parameter must contain an address value that is modulo 16. by the BC message sequence control processor, by means of the GP Flag Bits (FLG) instruction; and (3) GP0 and GP1 only (but none of the others) may be set or cleared by means of the BC message sequence control processor's Compare Frame Timer (CFT) or Compare Message Timer (CMT) instructions. The host processor also has read-only access to the BC condition codes by means of the BC CONDITION CODE REGISTER. Note that four (4) instructions are unconditional. These are Compare to Frame Timer (CFT), Compare to Message Timer (CMT), GP Flag Bits (FLG), and Execute and Flip (XQF). For these instructions, the Condition Code Field is "don't care". That is, these instructions are always executed, regardless of the result of the condition code test. All of the other instructions are conditional. That is, they will only be executed if the condition code specified by the condition code field in the op code word tests true. If the condition code field tests false, the instruction list pointer will skip down to the next instruction. As shown in TABLE 36, many of the operations include a singleword parameter. For an XEQ (execute message) operation, the parameter is a pointer to the start of the message's Control / Status block. For other operations, the parameter may be an address, a time value, an interrupt pattern, a mechanism to set or clear general purpose flag bits, or an immediate value. For several op codes, the parameter is "don't care" (not used). As described above, some of the op codes will cause the message sequence control processor to execute messages. In this case, the parameter references the first word of a message Control/Status block. With the exception of RT-to-RT transfer messages, all message status/control blocks are eight words long: a block control word, time-to-next-message parameter, data block pointer, command word, status word, loopback word, block status word, and time tag word. In the case of an RT-to-RT transfer message, the size of the message control/status block increases to 16 words. However, in this case, the last six words are not used; the ninth and tenth words are for the second command word and second status word. The third word in the message control/status block is a pointer that references the first word of the message's data word block. Note that the data word block stores only data words, which are to be either transmitted or received by the BC. By segregating data words from command words, status words, and other control and "housekeeping" functions, this architecture enables the use of convenient, usable data structures, such as circular buffers and double buffers. 8 1 7 0 6 1 5 0 4 3 2 1 0 OP CODES The instruction list pointer register references a pair of words in the BC instruction list: an op code word, followed by a parameter word. The format of the op code word, which is illustrated in FIGURE 4, includes a 5-bit op code field and a 5-bit condition code field. The op code identifies the instruction to be executed by the BC message sequence controller. Most of the operations are conditional, with execution dependent on the contents of the condition code field. Bits 3-0 of the condition code field identifies a particular condition. Bit 4 of the condition code field identifies the logic sense ("1" or "0") of the selected condition code on which the conditional execution is dependent. TABLE 36 lists all the op codes, along with their respective mnemonic, code value, parameter, and description. TABLE 37 defines all the condition codes. Eight of the condition codes (8 through F) are set or cleared as the result of the most recent message. The other eight are defined as "General Purpose" condition codes GP0 through GP7. There are three mechanisms for programming the values of the General Purpose Condition Code bits: (1) They may be set, cleared, or toggled by the host processor, by means of the BC GENERAL PURPOSE FLAG REGISTER; (2) they may be set, cleared, or toggled 15 Odd Parity 14 13 12 11 10 9 0 OpCode Field Condition Code Field FIGURE 4. BC OP CODE FORMAT Data Device Corporation www.ddc-web.com 18 BU-6174X/6184X/6186X M-12/04-0 TABLE 36. BC OPERATIONS FOR MESSAGE SEQUENCE CONTROL INSTRUCTION MNEMONIC Execute Message Jump XEQ OP CODE (HEX) 0001 CONDITIONAL DESCRIPTION OR UNCONDITIONAL Message Control / Conditional Executes the message at the specified Message Control/Status Status Block (See Note) Block Address if the condition flag tests TRUE, otherwise conAddress tinue execution at the next OpCode in the instruction list. PARAMETER Instruction List Address Instruction List Address Conditional Jump to the OpCode specified in the Instruction List if the condition flag tests TRUE, otherwise continue execution at the next OpCode in the instruction list. Jump to the OpCode specified by the Instruction List Address and push the Address of the Next OpCode on the Call Stack if the condition flag tests TRUE, otherwise continue execution at the next OpCode in the instruction list. Note that the maximum depth of the subroutine call stack is four. Return to the OpCode popped off the Call Stack if the condition flag tests TRUE, otherwise continue execution at the next OpCode in the instruction list. Generate an interrupt if the condition flag tests TRUE, otherwise continue execution at the next OpCode in the instruction list. The passed parameter (Interrupt Bit Pattern) specifies which of the ENHANCED BC IRQ bit(s) (bits 5-2) will be set in Interrupt Status Register #2. Only the four LSBs of the passed parameter are used. A parameter where the four LSBs are logic "0" will not generate an interrupt. Stop execution of the Message Sequence Control Program until a new BC Start is issued by the host if the condition flag tests TRUE, otherwise continue execution at the next OpCode in the instruction list. Delay the time specified by the Time parameter before executing the next OpCode if the condition flag tests TRUE, otherwise continue execution at the next OpCode without delay. The delay generated will use the Time to Next Message Timer. Wait until Frame Time counter is equal to Zero before continuing execution of the Message Sequence Control Program if the condition flag tests TRUE, otherwise continue execution at the next OpCode without delay. Compare Time Value to Frame Time Counter. The LT/GP0 and EQ/GP1 flag bits are set or cleared based on the results of the compare. If the value of the CFT's parameter is less than the value of the frame time counter, then the LT/GP0 and NE/GP1 flags will be set, while the GT-EQ/GP0 and EQ/GP1 flags will be cleared. If the value of the CFT's parameter is equal to the value of the frame time counter, then the GT-EQ/GP0 and EQ/GP1 flags will be set, while the LT/GP0 and NE/GP1 flags will be cleared. If the value of the CFT's parameter is greater than the current value of the frame time counter, then the GTEQ/GP0 and NE/GP1 flags will be set, while the LT/GP0 and EQ/GP1 flags will be cleared. Compare Time Value to Message Time Counter. The LT/GP0 and EQ/GP1 flag bits are set or cleared based on the results of the compare. If the value of the CMT's parameter is less than the value of the message time counter, then the LT/GP0 and NE/GP1 flags will be set, while the GT-EQ/GP0 and EQ/GP1 flags will be cleared. If the value of the CMT's parameter is equal to the value of the message time counter, then the GT-EQ/GP0 and EQ/GP1 flags will be set, while the LT/GP0 and NE/GP1 flags will be cleared. If the value of the CMT's parameter is greater than the current value of the message time counter, then the GT-EQ/GP0 and NE/GP1 flags will be set, while the LT/GP0 and EQ/GP1 flags will be cleared. JMP 0002 Subroutine Call CAL 0003 Conditional Subroutine Return Interrupt Request RTN 0004 Not Used (Don't Care) Interrupt Bit Pattern in 4 LS bits Conditional IRQ 0006 Conditional Halt HLT 0007 Not Used (Don't Care) Conditional Delay DLY 0008 Delay Time Value (Resolution = 1S / LSB) Not Used (Don't Care) Conditional Wait Until Frame Timer =0 Compare to Frame Timer WFT 0009 Conditional CFT 000A Delay Time Value (Resolution = 100S / LSB) Unconditional Compare to Message Timer CMT 000B Delay Time Value (Resolution = 1S / LSB) Unconditional NOTE: While the XEQ (Execute Message) instruction is conditional, not all condition codes may be used to enable its use. The ALWAYS and NEVER condition codes may be used. The eight general purpose flag bits, GP0 through GP7, may also be used. However, if GP0 through GP7 are used, it is imperative that the host processor not modify the value of the specific general purpose flag bit that enabled a particular message while that message is being processed. Similarly, the LT, GT-EQ, EQ, and NE flags, which the BC only updates by means of the CFT and CMT instructions, may also be used. However, these two flags are dual use. Therefore, if these are used, it is imperative that the host processor not modify the value of the specific flag (GP0 or GP1) that enabled a particular message while that message is being processed. The NORESP, FMT ERR, GD BLK XFER, MASKED STATUS SET, BAD MESSAGE, RETRY0, and RETRY1 condition codes are not available for use with the XEQ instruction and should not be used to enable its execution. Data Device Corporation www.ddc-web.com 19 BU-6174X/6184X/6186X M-12/04-0 TABLE 36. BC OPERATIONS FOR MESSAGE SEQUENCE CONTROL (CONT.) INSTRUCTION GP Flag Bits MNEMONIC FLG OP CODE (HEX) 000C PARAMETER Used to set, clear, or toggle GP (General Purpose) Flag bits (See description) CONDITIONAL OR UNCONDITIONAL Unconditional DESCRIPTION Used to set, toggle, or clear any or all of the eight general purpose flags. The table below illustrates the use of the GP Flag Bits instruction for the case of GP0 (General Purpose Flag 0). Bits 1 and 9 of the parameter byte affect flag GP1, bits 2 and 10 effect GP2, etc., according to the following rules: Bit 8 0 0 1 1 Load Time Tag Counter LTT 000D Time Value. Resolution (s/LSB) is defined by bits 9, 8, and 7 of Configuration Register #2. Time Value (resolution = 100 s/LSB) Not Used (Don't Care) Not Used (Don't Care) Conditional Bit 0 0 1 0 1 Effect on GP0 No Change Set Flag Clear Flag Toggle Flag Load Time Tag Counter with Time Value if the condition flag tests TRUE, otherwise continue execution at the next OpCode in the instruction list. Load Frame Timer Start Frame Timer Push Time Tag Register LFT 000E Conditional Load Frame Timer Register with the Time Value parameter if the condition flag tests TRUE, otherwise continue execution at the next OpCode in the instruction list. Start Frame Time Counter with Time Value in Time Frame register if the condition flag tests TRUE, otherwise continue execution at the next OpCode in the instruction list. Push the value of the Time Tag Register on the General Purpose Queue if the condition flag tests TRUE, otherwise continue execution at the next OpCode in the instruction list. Push the Block Status Word for the most recent message on the General Purpose Queue if the condition flag tests TRUE, otherwise continue execution at the next OpCode in the instruction list. Push Immediate data on the General Purpose Queue if the condition flag tests TRUE, otherwise continue execution at the next OpCode in the instruction list. Push the data stored at the specified memory location on the General Purpose Queue if the condition flag tests TRUE, otherwise continue execution at the next OpCode in the instruction list. Wait for a logic "0"-to-logic "1" transition on the EXT_TRIG input signal before proceeding to the next OpCode in the instruction list if the condition flag tests TRUE, otherwise continue execution at the next OpCode without delay. Execute (unconditionally) the message referenced by the Message Control/Status Block Address. Following the processing of this message, if the condition flag tests TRUE, the BC will toggle bit 4 in the Message Control/Status Block Address, and store the new Message Block Address as the updated value of the parameter following the XQF instruction code. As a result, the next time that this line in the instruction list is executed, the Message Control/Status Block at the updated address (old address XOR 0010h), rather than the old address, will be processed. If the condition flag tests FALSE, the value of the Message Control/Status Block Address parameter will not change. SFT 000F Conditional PTT 0010 Conditional Push Block Status Word PBS 0011 Not Used (Don't Care) Conditional Push Immediate Value Push Indirect PSI 0012 Immediate Value Conditional PSM 0013 Memory Address Conditional Wait for External Trigger Execute and Flip WTG 0014 Not Used (Don't Care) Conditional XQF 0015 Message Control / Status Block Address Unconditional Data Device Corporation www.ddc-web.com 20 BU-6174X/6184X/6186X M-12/04-0 TABLE 37. BC CONDITION CODES BIT CODE 0 NAME (BIT 4 = 0) LT/GP0 INVERSE (BIT 4 = 1) GT-EQ/ GP0 FUNCTIONAL DESCRIPTION Less than or GP0 flag. This bit is set or cleared based on the results of the compare. If the value of the CMT's parameter is less than the value of the message time counter, then the LT/GP0 and NE/GP1 flags will be set, while the GT-EQ/GP0 and EQ/GP1 flags will be cleared. If the value of the CMT's parameter is equal to the value of the message time counter, then the GT-EQ/GP0 and EQ/GP1 flags will be set, while the LT/GP0 and NE/GP1 flags will be cleared. If the value of the CMT's parameter is greater than the current value of the message time counter, then the GT-EQ/GP0 and NE/GP1 flags will be set , while the LT/GP0 and EQ/GP1 flags will be cleared. Also, General Purpose Flag 1 may be also be set or cleared by a FLG operation. Equal Flag. This bit is set or cleared after CFT or CMT operation. If the value of the CMT's parameter is equal to the value of the message time counter, then the EQ/GP1 flag will be set and the NE/GP1 bit will be cleared. If the value of the CMT's parameter is not equal to the value of the message time counter, then the NE/GP1 flag will be set and the EQ/GP1bit will be cleared. Also, General Purpose Flag 1 may be also be set or cleared by a FLG operation. General Purpose Flags may be set, cleared, or toggled by a FLG operation. The host processor can set, clear, or toggle these flags in the same way as the FLG instruction by means of the BC GENERAL PURPOSE FLAG REGISTER. 1 EQ/GP1 NE/GP1 2 3 4 5 6 7 8 GP2 GP3 GP4 GP5 GP6 GP7 NORESP GP2 GP3 GP4 GP5 GP6 GP7 RESP NORESP indicates that an RT has either not responded or has responded later than the BC No Response Timeout time. The Enhanced Mini-ACE's/-ACE's No Response Timeout Time is defined per MIL-STD-1553B as the time from the mid-bit crossing of the parity bit of the last word transmitted by the BC to the mid-sync crossing of the RT Status Word. The value of the No Response Timeout value is programmable from among the nominal values 18.5, 22.5, 50.5, and 130 s (1 s) by means of bits 10 and 9 of Configuration Register #5. FMT ERR indicates that the received portion of the most recent message contained one or more violations of the 1553 message validation criteria (sync, encoding, parity, bit count, word count, etc.), or the RT's status word received from a responding RT contained an incorrect RT address field. For the most recent message, GD BLK XFER will be set to logic "1" following completion of a valid (error-free) RT-to-BC transfer, RT-to-RT transfer, or transmit mode code with data message. This bit is set to logic "0" following an invalid message. GOOD DATA BLOCK TRANSFER is always logic "0" following a BC-to-RT transfer, a mode code with data, or a mode code without data. The Loop Test has no effect on GOOD DATA BLOCK TRANSFER. GOOD DATA BLOCK TRANSFER may be used to determine if the transmitting portion of an RT-to-RT transfer was error free. Indicates that one or both of the following conditions have occurred for the most recent message: (1) If one (or more) of the Status Mask bits (14 through 9) in the BC Control Word is logic "0" and the corresponding bit(s) is (are) set (logic "1") in the received RT Status Word. In the case of the RESERVED BITS MASK (bit 9) set to logic "0", any or all of the 3 Reserved Status Word bits being set will result in a MASKED STATUS SET condition; and/or (2) If BROADCAST MASK ENABLED/XOR (bit 11 of Configuration Register #4) is logic "1" and the MASK BROADCAST bit of the message's BC Control Word is logic "0" and the BROADCAST COMMAND RECEIVED bit in the received RT Status Word is logic "1". BAD MESSAGE indicates either a format error, loop test fail, or no response error for the most recent message. Note that a "Status Set" condition has no effect on the "BAD MESSAGE/GOOD MESSAGE" condition code. These two bits reflect the retry status of the most recent message. The number of times that the message was retried is delineated by these two bits as shown below: RETRY COUNT 1 RETRY COUNT 0 Number of (bit 14) (bit 13) Message Retries 0 0 0 0 1 1 1 0 N/A 1 1 2 The ALWAYS bit should be set (bit 4 = 0) to designate an instruction as unconditional. The NEVER bit (bit 4 = 0) can be used to implement an NOP or "skip" instruction. 9 FMT ERR FMT ERR A GD BLK XFER GD BLK XFER B MASKED STATUS BIT MASKED STATUS BIT C BAD MESSAGE RETRY0 RETRY1 GOOD MESSAGE RETRY0 RETRY1 D E F ALWAYS NEVER Data Device Corporation www.ddc-web.com 21 BU-6174X/6184X/6186X M-12/04-0 Other operations support program flow control; i.e., jump and call capability. The call capability includes maintenance of a call stack which supports a maximum of four (4) entries; there is also a return instruction. In the case of a call stack overrun or underrun, the BC will issue a CALL STACK POINTER REGISTER ERROR interrupt, if enabled. Other op codes may be used to delay for a specified time; start a new BC frame; wait for an external trigger to start a new frame; perform comparisons based on frame time and time-to-next message; load the time tag or frame time registers; halt; and issue host interrupts. In the case of host interrupts, the message control processor passes a 4-bit user-defined interrupt vector to the host, by means of the Enhanced Mini-ACE/-ACE's Interrupt Status Register. The purpose of the FLG instruction is to enable the message sequence controller to set, clear, or toggle the value(s) of any or all of the eight general purpose condition flags. The op code parity bit encompasses all sixteen bits of the op code word. This bit must be programmed for odd parity. If the message sequence control processor fetches an undefined op code word, an op code word with even parity, or bits 9-5 of an op code word do not have a binary pattern of 01010, the message sequence control processor will immediately halt the BC's operation. In addition, if enabled, a BC TRAP OP CODE interrupt will be issued. Also, if enabled, a parity error will result in an OP CODE PARITY ERROR interrupt. TABLE 37 describes the Condition Codes. BC MESSAGE SEQUENCE CONTROL The Enhanced Mini-ACE/-ACE BC message sequence control capability enables a high degree of offloading of the host processor. This includes using the various timing functions to enable autonomous structuring of major and minor frames. In addition, by implementing conditional jumps and subroutine calls, the message sequence control processor greatly simplifies the insertion of asynchronous, or "out-of-band" messages. Execute and Flip Operation. The Enhanced Mini-ACE/-ACE BC's XQF, or "Execute and Flip" operation, provides some unique capabilities. Following execution of this unconditional instruction, if the condition code tests TRUE, the BC will modify the value of the current XQF instruction's pointer parameter by toggling bit 4 of the pointer. That is, if the selected condition flag tests true, the value of the parameter will be updated to the value = old address XOR 0010h. As a result, the next time that this line in the instruction list is executed, the Message Control/Status Block at the updated address (old address XOR 0010h) will be processed, rather than the one at the old address. The operation of the XQF instruction is illustrated in FIGURE 5. There are multiple ways of utilizing the "execute and flip" instruction. One is to facilitate the implementation of a double buffering data scheme for individual messages. This allows the message sequence control processor to "ping-pong" between a pair of data buffers for a particular message. By doing so, the host processor can access one of the two Data Word blocks, while the BC reads or writes the alternate Data Word block. A second application of the "execute and flip" capability is in conjunction with message retries. This allows the BC to not only switch buses when retrying a failed message, but to automatically switch buses permanently for all future times that the same message is to be processed. This not only provides a high degree of autonomy from the host CPU, but saves BC bandwidth, by eliminating the need for future attempts to process messages on an RT's failed channel. (part of) BC INSTRUCTION LIST XQF POINTER MESSAGE CONTROL/STATUS BLOCK 0 XX00h POINTER DATA BLOCK 0 MESSAGE CONTROL/STATUS BLOCK 1 XX00h POINTER DATA BLOCK 1 FIGURE 5. EXECUTE and FLIP (XQF) OPERATION Data Device Corporation www.ddc-web.com 22 BU-6174X/6184X/6186X M-12/04-0 General Purpose Queue. The Enhanced Mini-ACE/-ACE BC allows for the creation of a general purpose queue. This data structure provides a means for the message sequence processor to convey information to the BC host. The BC op code repertoire provides mechanisms to push various items on this queue. These include the contents of the Time Tag Register, the Block Status Word for the most recent message, an immediate data value, or the contents of a specified memory address. FIGURE 6 illustrates the operation of the BC General Purpose Queue. Note that the BC General Purpose Queue Pointer Register will always point to the next address location (modulo 64); that is, the location following the last location written by the BC message sequence control engine. If enabled, a BC GENERAL PURPOSE QUEUE ROLLOVER interrupt will be issued when the value of the queue pointer address rolls over at a 64-word boundary. The rollover will always occur at a modulo 64 address. REMOTE TERMINAL (RT) ARCHITECTURE The Enhanced Mini-ACE/-ACE's RT architecture builds upon that of the ACE and Mini-ACE. The Enhanced Mini-ACE/-ACE provides multiprotocol support, with full compliance to all of the commonly used data bus standards, including MIL-STD-1553A, MIL-STD-1553B Notice 2, STANAG 3838, General Dynamics 16PP303, and McAirA3818, A5232, and A5690. For the Enhanced Mini-ACE/-ACE RT mode, there is programmable flexibility enabling the RT to be configured to fulfill any set of system requirements. This includes the capability to meet the MILSTD-1553A response time requirement of 2 to 5 s, and multiple options for mode code subaddresses, mode codes, RT status word, and RT BIT word. BC GENERAL PURPOSE QUEUE (64 Locations) LAST LOCATION BC GENERAL PURPOSE QUEUE POINTER REGISTER NEXT LOCATION FIGURE 6. BC GENERAL PURPOSE QUEUE Data Device Corporation www.ddc-web.com 23 BU-6174X/6184X/6186X M-12/04-0 The Enhanced Mini-ACE/-ACE RT protocol design implements all of the MIL-STD-1553B message formats and dual redundant mode codes. The design has passed validation testing for MILSTD-1553B compliance. The Enhanced Mini-ACE/-ACE RT performs comprehensive error checking including word and format validation, and checks for various RT-to-RT transfer errors. One of the main features of the Enhanced Mini-ACE/-ACE RT is its choice of memory management options. These include single buffering by subaddress, double buffering for individual receive subaddresses, circular buffering by individual subaddresses, and global circular buffering for multiple (or all) subaddresses. Other features of the Enhanced Mini-ACE/-ACE RT include a set of interrupt conditions, a flexible status queue with filtering based on valid and/or invalid messages, flexible command illegalization, programmable busy by subaddress, multiple options on time tagging, and an "auto-boot" feature which allows the RT to initialize as an online RT with the busy bit set following power turn-on. (hex) for the Area A Stack Pointer and address 0104 for the Area B Stack Pointer. In addition to the Stack Pointer, there are several other areas of the shared RAM address space that are designated as fixed locations (all shown in bold). These are for the Area A and Area B lookup tables, the illegalization lookup table, the busy lookup table, and the mode code data tables. The RT lookup tables (reference TABLE 39) provide a mechanism for allocating data blocks for individual transmit, receive, or broadcast subaddresses. The RT lookup tables include subaddress control words as well as the individual data block pointers. If command illegalization is used, address range 0300-03FF is used for command illegalizing. The descriptor stack RAM area, as well as the individual data blocks, may be located in any of the non-fixed areas in the shared RAM address space. Note that in TABLE 38, there is no area allocated for "Stack B". This is shown for purpose of simplicity of illustration. Also, note that in TABLE 38, the allocated area for the RT command stack is 256 words. However, larger stack sizes are possible. That is, the RT command stack size may be programmed for 256 words (64 messages), 512, 1024, or 2048 words (512 messages) by means of bits 14 and 13 of Configuration Register 3. RT MEMORY ORGANIZATION TABLE 38 illustrates a typical memory map for an Enhanced MiniACE/-ACE RT with 4K RAM. The two Stack Pointers reside in fixed locations in the shared RAM address space: address 0100 TABLE 38. TYPICAL RT MEMORY MAP (SHOWN FOR 4K RAM) ADDRESS (HEX) 0000-00FF 0100 0101 0102-0103 0104 0105 0106-0107 0108-010F 0110-013F 0140-01BF 01C0-023F 0240-0247 0248-025F 0260-027F 0280-02FF 0300-03FF 0400-041F 0420-043F * * * 0FE0-0FFF DESCRIPTION Stack A Stack Pointer A Global Circular Buffer A Pointer RESERVED Stack Pointer B Global Circular Buffer B Pointer RESERVED Mode Code Selective Interrupt Table Mode Code Data Lookup Table A Lookup Table B Busy Bit Lookup Table (not used) Data Block 0 Data Block 1-4 Command Illegalizing Table Data Block 5 Data Block 6 * * * Data Block 100 AREA A 0140 * * * 015F 0160 * * * 017F 0180 * * * 019F 01A0 * * * 01BF TABLE 39. RT LOOK-UP TABLES AREA B 01C0 * * * 01DF 01E0 * * * 01FF 0200 * * * 021F 0220 * * * 023F DESCRIPTION Rx(/Bcst) SA0 * * * Rx(/Bcst) SA31 Tx SA0 * * * Tx SA31 Bcst SA0 * * * Bcst SA31 SACW SA0 * * * SACW SA31 COMMENT Receive (/Broadcast) Lookup Pointer Table Transmit Lookup Pointer Table Broadcast Lookup Pointer Table (Optional) Subaddress Control Word Lookup Table (Optional) Data Device Corporation www.ddc-web.com 24 BU-6174X/6184X/6186X M-12/04-0 RT MEMORY MANAGEMENT The Enhanced Mini-ACE/-ACE provides a variety of RT memory management capabilities. As with the ACE and Mini-ACE, the choice of memory management scheme is fully programmable on a transmit/receive/broadcast subaddress basis. In compliance with MIL-STD-1553B Notice 2, received data from broadcast messages may be optionally separated from nonbroadcast received data. For each transmit, receive or broadcast subaddress, either a single-message data block, a double buffered configuration (two alternating Data Word blocks), or a variable-sized (128 to 8192 words) subaddress circular buffer may be allocated for data storage. The memory management scheme for individual subaddresses is designated by means of the subaddress control word (reference TABLE 40). For received data, there is also a global circular buffer mode. In this configuration, the data words received from multiple (or all) subaddresses are stored in a common circular buffer structure. Like the subaddress circular buffer, the size of the global circular buffer is programmable, with a range of 128 to 8192 data words. The double buffering feature provides a means for the host processor to easily access the most recent, complete received block of valid Data Words for any given subaddress. In addition to helping ensure data sample consistency, the circular buffer options provide a means for greatly reducing host processor overhead for multi-message bulk data transfer applications. End-of-message interrupts may be enabled either globally (following all messages), following error messages, on a transmit/receive/broadcast subaddress or mode code basis, or when a circular buffer reaches its midpoint (50% boundary) or lower (100%) boundary. A pair of interrupt status registers allow the host processor to determine the cause of all interrupts by means of a single read operation. SINGLE BUFFERED MODE The operation of the single buffered RT mode is illustrated in FIGURE 7. In the single buffered mode, the respective lookup table entry must be written by the host processor. Received data words are written to, or transmitted data words are read from the data word block with starting address referenced by the lookup table pointer. In the single buffered mode, the current lookup table pointer is not updated by the Enhanced Mini-ACE/-ACE memory management logic. Therefore, if a subsequent message is received for the same subaddress, the same Data Word block will be overwritten or overread. SUBADDRESS DOUBLE BUFFERING MODE The Enhanced Mini-ACE/-ACE provides a double buffering mechanism for received data, that may be selected on an individual subaddress basis for any or all receive (and/or broadcast) subaddresses. This is illustrated in FIGURE 8. It should be noted that the Subaddress Double Buffering mode is applicable for receive data only, not for transmit data. Double buffering of transmit messages may be easily implemented by software techniques. TABLE 40. RT SUBADDRESS CONTROL WORD - MEMORY MANAGEMENT OPTIONS DOUBLE-BUFFERED OR GLOBAL CIRCULAR BUFFER (bit 15) 0 1 0 0 0 0 0 0 0 SUBADDRESS CONTROL WORD BITS MM2 0 0 0 0 0 1 1 1 1 MM1 0 0 0 1 1 0 0 1 1 MM0 0 0 1 0 1 0 1 0 1 MEMORY MANAGEMENT SUBADDRESS BUFFER SCHEME DESCRIPTION Single Message For Receive or Broadcast: Double Buffered For Transmit: Single Message 128-Word 256-Word 512-Word 1024-Word 2048-Word 4096-Word 8192-Word (for receive and / or broadcast subaddresses only) 1 1 1 1 Global Circular Buffer: The buffer size is specified by Configuration Register #6, bits 11-9. The pointer to the global circular buffer is stored at address 0101 (for Area A) or address 0105 (for Area B) Subaddress specific circular buffer of specified size. Data Device Corporation www.ddc-web.com 25 BU-6174X/6184X/6186X M-12/04-0 The purpose of the subaddress double buffering mode is to provide data sample consistency to the host processor. This is accomplished by allocating two 32-word data word blocks for each individual receive (and/or broadcast receive) subaddress. At any given time, one of the blocks will be designated as the "active" 1553 block while the other will be considered as "inactive". The data words for the next receive command to that subaddress will be stored in the active block. Following receipt of a valid message, the Enhanced Mini-ACE/-ACE will automatically switch the active and inactive blocks for that subaddress. As a result, the latest, valid, complete data block is always accessible to the host processor. In general, the location after the last data word written or read (modulo the circular buffer size) during the message is written to the respective lookup table location during the end-of-message sequence. By so doing, data for the next message for the respective transmit, receive(/broadcast), or broadcast subaddress will be accessed from the next lower contiguous block of locations in the circular buffer. For the case of a receive (or broadcast receive) message with a data word error, there is an option such that the lookup table pointer will only be updated following receipt of a valid message. That is, the pointer will not be updated following receipt of a message with an error in a data word. This allows failed messages in a bulk data transfer to be retried without disrupting the circular buffer data structure, and without intervention by the RT's host processor. CIRCULAR BUFFER MODE The operation of the Enhanced Mini-ACE/-ACE's circular buffer RT memory management mode is illustrated in FIGURE 9. As in the single buffered and double buffered modes, the individual lookup table entries are initially loaded by the host processor. At the start of each message, the lookup table entry is stored in the third position of the respective message block descriptor in the descriptor stack area of RAM. Receive or transmit data words are transferred to (from) the circular buffer, starting at the location referenced by the lookup table pointer. GLOBAL CIRCULAR BUFFER Beyond the programmable choice of single buffer mode, double buffer mode, or circular buffer mode, programmable on an individual subaddress basis, the Enhanced Mini-ACE/-ACE RT architecture provides an additional option, a variable sized global circular buffer. The Enhanced Mini-ACE/-ACE RT allows for a CONFIGURATION REGISTER STACK POINTERS DESCRIPTOR STACKS LOOK-UP TABLE (DATA BLOCK ADDR) 15 13 0 DATA BLOCKS CURRENT AREA B/A BLOCK STATUS WORD TIME TAG WORD DATA BLOCK POINTER RECEIVED COMMAND WORD LOOK-UP TABLE ADDR (See note) DATA BLOCK DATA BLOCK Note: Lookup table is not used for mode commands when enhanced mode codes are enabled. FIGURE 7. RT SINGLE BUFFERED MODE Data Device Corporation www.ddc-web.com BU-6174X/6184X/6186X M-12/04-0 26 mix of single buffered, double buffered, and individually circular buffered subaddresses, along with the use of the global double buffer for any arbitrary group of receive(/broadcast) or broadcast subaddresses. In the global circular buffer mode, the data for multiple receive subaddresses is stored in the same circular buffer data structure. The size of the global circular buffer may be programmed for 128, 256, 512, 1024, 2048, 4096, or 8192 words, by means of bits 11, 10, and 9 of Configuration Register #6. As shown in TABLE 40, individual subaddresses may be mapped to the global circular buffer by means of their respective subaddress control words. The pointer to the Global Circular Buffer will be stored in location 0101 (for Area A), or location 0105 (for Area B). The global circular buffer option provides a highly efficient method for storing received message data. It allows for frequently used subaddresses to be mapped to individual data blocks, while also providing a method for asynchronously received messages to infrequently used subaddresses to be logged to a common area. Alternatively, the global circular buffer provides an efficient means for storing the received data words for all subaddresses. Under this method, all received data words are stored chronologically, regardless of subaddress. CONFIGURATION REGISTER STACK POINTERS DESCRIPTOR STACK LOOK-UP TABLES 15 13 0 DATA BLOCKS CURRENT AREA B/A BLOCK STATUS WORD X..X 0 YYYYY TIME TAG WORD DATA BLOCK POINTER RECEIVED COMMAND WORD DATA BLOCK POINTER X..X 1 YYYYY DATA BLOCK 1 DATA BLOCK 0 RECEIVE DOUBLE BUFFER ENABLE MSB SUBADDRESS CONTROL WORD FIGURE 8. RT DOUBLE BUFFERED MODE CONFIGURATION REGISTER STACK POINTERS DESCRIPTOR STACK LOOK-UP TABLES CIRCULAR DATA BUFFER 15 13 0 CURRENT AREA B/A BLOCK STATUS WORD TIME TAG WORD DATA BLOCK POINTER RECEIVED COMMAND WORD LOOK-UP TABLE ADDRESS POINTER TO CURRENT DATA BLOCK LOOK-UP TABLE ENTRY POINTER TO NEXT DATA BLOCK * RECEIVED (TRANSMITTED) MESSAGE DATA (NEXT LOCATION) 128, 256 8192 WORDS Notes: 1. TX/RS/BCST_SA look-up table entry is updated following valid receive (broadcast) message or following completion of transit message 2. For the Global Circular Buffer Mode, the pointer is read from and re-written to Address 0101 (for Area A) or Address 0105 (for Area B). CIRCULAR BUFFER ROLLOVER FIGURE 9. RT CIRCULAR BUFFERED MODE Data Device Corporation www.ddc-web.com 27 BU-6174X/6184X/6186X M-12/04-0 RT DESCRIPTOR STACK The descriptor stack provides a chronology of all messages processed by the Enhanced Mini-ACE/-ACE RT. Reference FIGURES 7, 8, and 9. Similar to BC mode, there is a four-word block descriptor in the Stack for each message processed. The four entries to each block descriptor are the Block Status Word, Time Tag Word, the pointer to the start of the message's data block, and the 16-bit received Command Word. The RT Block Status Word includes indications of whether a particular message is ongoing or has been completed, what bus channel it was received on, indications of illegal commands, and flags denoting various message error conditions. For the double buffering, subaddress circular buffering, and global circular buffering modes, the data block pointer may be used for locating the data blocks for specific messages. Note that for mode code commands, there is an option to store the transmitted or received data word as the third word of the descriptor, in place of the data block pointer. The Time Tag Word provides a 16-bit indication of relative time for individual messages. The resolution of the Enhanced MiniACE/-ACE's time tag is programmable from among 2, 4, 8, 16, 32, or 64 s/LSB. There is also a provision for using an external clock input for the time tag (consult factory). If enabled, there is a time tag rollover interrupt, which is issued when the value of the time tag rolls over from FFFF(hex) to 0. Other time tag options include the capabilities to clear the time tag register following receipt of a Synchronize (without data) mode command and/or to set the time tag following receipt of a Synchronize (with data) mode command. For the latter, there is an added option to filter the "set" capability based on the LSB of the received data word being equal to logic "0". (3) Monitor command (descriptor) stack; and (4) Monitor data stack. The 50% rollover interrupt is beneficial for performing bulk data transfers. For example, when using circular buffering for a particular receive subaddress, the 50% rollover interrupt will inform the host processor when the circular buffer is half full. At that time, the host may proceed to read the received data words in the upper half of the buffer, while the Enhanced Mini-ACE/-ACE RT writes received data words to the lower half of the circular buffer. Later, when the RT issues a 100% circular buffer rollover interrupt, the host can proceed to read the received data from the lower half of the buffer, while the Enhanced Mini-ACE RT continues to write received data words to the upper half of the buffer. Interrupt status queue. The Enhanced Mini-ACE/-ACE RT, Monitor, and combined RT/Monitor modes include the capability for generating an interrupt status queue. As illustrated in FIGURE 11, this provides a chronological history of interrupt generating events and conditions. In addition to the Interrupt Mask Register, the Interrupt Status Queue provides additional filtering capability, such that only valid messages and/or only invalid messages may result in the creation of an entry to the Interrupt Status Queue. Queue entries for invalid and/or valid messages may be disabled by means of bits 8 and 7 of configuration register #6. The interrupt status queue is 64 words deep, providing the capability to store entries for up to 32 messages. These events and conditions include both message-related and non-message related events. Note that the Interrupt Vector Queue Pointer Register will always point to the next location (modulo 64) following the last vector/pointer pair written by the Enhanced Mini-ACE/-ACE RT. The pointer to the Interrupt Status Queue is stored in the INTERRUPT VECTOR QUEUE POINTER REGISTER (register address 1F). This register must be initialized by the host, and is subsequently incremented by the RT message processor. The interrupt status queue is 64 words deep, providing the capability to store entries for up to 32 messages. The queue rolls over at addresses of modulo 64. The events that result in queue entries include both message-related and nonmessage-related events. Note that the Interrupt Vector Queue Pointer Register will always point to the next location (modulo 64) following the last vector/pointer pair written by the Enhanced Mini-ACE/-ACE RT, Monitor, or RT/Monitor. Each event that causes an interrupt results in a two-word entry to be written to the queue. The first word of the entry is the interrupt vector. The vector indicates which interrupt event(s)/condition(s) caused the interrupt. The interrupt events are classified into two categories: message interrupt events and non-message interrupt events. Messagebased interrupt events include End-of-Message, Selected mode BU-6174X/6184X/6186X M-12/04-0 RT INTERRUPTS The Enhanced Mini-ACE/-ACE offers a great deal of flexibility in terms of RT interrupt processing. By means of the Enhanced MiniACE/-ACE's two Interrupt Mask Registers, the RT may be programmed to issue interrupt requests for the following events/conditions: End-of-(every)Message, Message Error, Selected (transmit or receive) Subaddress, 100% Circular Buffer Rollover, 50% Circular Buffer Rollover, 100% Descriptor Stack Rollover, 50% Descriptor Stack Rollover, Selected Mode Code, Transmitter Timeout, Illegal Command, and Interrupt Status Queue Rollover. Interrupts for 50% Rollovers of Stacks and Circular Buffers. The Enhanced Mini-ACE/-ACE RT and Monitor are capable of issuing host interrupts when a subaddress circular buffer pointer or stack pointer crosses its mid-point boundary. For RT circular buffers, this is applicable for both transmit and receive subaddresses. Reference FIGURE 10. There are four interrupt mask and interrupt status register bits associated with the 50% rollover function: (1) RT circular buffer; (2) RT command (descriptor) stack; Data Device Corporation www.ddc-web.com 28 code, Format error, Subaddress control word interrupt, RT Circular buffer Rollover, Handshake failure, RT Command stack rollover, transmitter timeout, MT Data Stack rollover, MT Command Stack rollover, RT Command Stack 50% rollover, MT Data Stack 50% rollover, MT Command Stack 50% rollover, and RT Circular buffer 50% rollover. Non-message interrupt events/conditions include time tag rollover, RT address parity error, RAM parity error, and BIT completed. Bit 0 of the interrupt vector (interrupt status) word indicates whether the entry is for a message interrupt event (if bit 0 is logic "1") or a non-message interrupt event (if bit 0 is logic "0"). It is not possible for one entry on the queue to indicate both a message interrupt and a non-message interrupt. As illustrated in FIGURE 11, for a message interrupt event, the parameter word is a pointer. The pointer will reference the first word of the RT or MT command stack descriptor (i.e., the Block Status Word). For a RAM Parity Error non-message interrupt, the parameter will be the RAM address where the parity check failed. For the RT address Parity Error, Protocol Self-test Complete, and Time Tag rollover non-message interrupts, the parameter is not used; it will have a value of 0000. DESCRIPTOR STACK BLOCK STATUS WORD TIME TAG WORD DATA BLOCK POINTER RECEIVED COMMAND WORD LOOK-UP TABLE CIRCULAR BUFFER* (128,256,...8192 WORDS) DATA POINTER RECEIVED (TRANSMITTED) MESSAGE DATA 50% 50% ROLLOVER INTERRUPT Note The example shown is for an RT Subaddress Circular Buffer. The 50% and 100% Rollover Interrupts are also applicable to the RT Global Circulat Buffer, RT Command Stack, Monitor Command Stack, and Monitor Data Stack. 100% 100% ROLLOVER INTERRUPT FIGURE 10. 50% and 100% ROLLOVER INTERRUPTS INTERRUPT STATUS QUEUE (64 Locations) DESCRIPTOR STACK INTERRUPT VECTOR PARAMETER (POINTER) INTERRUPT VECTOR QUEUE POINTER REGISTER (IF) NEXT VECTOR BLOCK STATUS WORD TIME TAG DATA BLOCK POINTER RECEIVED COMMAND DATA WORD BLOCK FIGURE 11. RT (and MONITOR) INTERRUPT STATUS QUEUE (shown for message Interrupt event) Data Device Corporation www.ddc-web.com 29 BU-6174X/6184X/6186X M-12/04-0 If enabled, an INTERRUPT STATUS QUEUE ROLLOVER interrupt will be issued when the value of the queue pointer address rolls over at a 64-word address boundary. ibility, allowing any subset of the 4096 possible combinations of broadcast/own address, T/R bit, subaddress, and word count/mode code to be illegalized. The address map of the Enhanced Mini-ACE/-ACE's illegalizing table is illustrated in TABLE 41. NOTE: Please see Appendix "F" of the Enhanced Mini-ACE User's Guide for important information applicable only to RT MODE operation, enabling of the interrupt status queue and use of specific non-message interrupts. RT COMMAND ILLEGALIZATION The Enhanced Mini-ACE/-ACE provides an internal mechanism for RT Command Word illegalizing. By means of a 256-word area in shared RAM, the host processor may designate that any message be illegalized, based on the command word T/R bit, subaddress, and word count/mode code fields. The Enhanced MiniACE/-ACE illegalization scheme provides the maximum in flex- BUSY BIT The Enhanced Mini-ACE/-ACE RT provides two different methods for setting the Busy status word bit: (1) globally, by means of Configuration Register #1; or (2) on a T/R-bit/subaddress basis, by means of a RAM lookup table. If the host CPU asserts the BUSY bit to logic "0" in Configuration Register #1, the Enhanced Mini-ACE/-ACE RT will respond to all non-broadcast commands with the Busy bit set in its RT Status Word. Alternatively, there is a Busy lookup table in the Enhanced MiniACE/-ACE shared RAM. By means of this table, it is possible for the TABLE 41. ILLEGALIZATION TABLE MEMORY MAP ADDRESS 300 301 302 303 * * * 33F 340 341 342 * * * 37D 37E 37F 380 381 382 383 * * * 3BE 3BF 3C0 3C1 3C2 3C3 * * * 3FC 3FD 3FE 3FF DESCRIPTION Brdcst / Rx, SA 0. MC15-0 Brdcst / RX, SA 0. MC31-16 Brdcst / Rx, SA 1. WC15-0 Brdcst / Rx, SA 1. WC31-16 * * * Brdcst / Rx, SA 31. MC31-16 Brdcst / Tx, SA 0. MC15-0 Brdcst / Tx, SA 0.MC31-16 Brdcst / Tx, SA 1. WC15-0 * * * Brdcst / Tx, SA 30. WC31-16 Brdcst / Tx, SA 31. MC15-0 Brdcst / Tx, SA 31. MC31-16 Own Addr / Rx, SA 0. MC15-0 Own Addr / Rx, SA 0. MC31-16 Own Addr / Rx, SA 1. WC15-0 Own Addr / Rx, SA 1. WC31-16 * * * Own Addr / Rx, SA 31. MC15-0 Own Addr / Rx, SA 31. MC31-16 Own Addr / Tx, SA 0. MC15-0 Own Addr / Tx, SA 0. MC31-16 Own Addr / Tx, SA 1. WC15-0 Own Addr / Tx, SA 1. WC31-16 * * * Own Addr / Tx, SA 30. WC15-0 Own Addr / Tx, SA 30. WC31-16 Own Addr / Tx, SA 31. MC15-0 Own Addr / Tx, SA 31. MC31-16 Data Device Corporation www.ddc-web.com 30 BU-6174X/6184X/6186X M-12/04-0 host processor to set the busy bit for any selectable subset of the 128 combinations of broadcast/own address, T/R bit, and subaddress. If the busy bit is set for a transmit command, the Enhanced MiniACE/-ACE RT will respond with the busy bit set in the status word, but will not transmit any data words. If the busy bit is set for a receive command, the RT will also respond with the busy status bit set. There are two programmable options regarding the reception of data words for a non-mode code receive command for which the RT is busy: (1) to transfer the received data words to shared RAM; or (2) to not transfer the data words to shared RAM. TABLE 42. RT BIT WORD BIT 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB) DESCRIPTION LOOP TEST FAILURE B LOOP TEST FAILURE A HANDSHAKE FAILURE TRANSMITTER SHUTDOWN B TRANSMITTER SHUTDOWN A TERMINAL FLAG INHIBITED BIT TEST FAILURE HIGH WORD COUNT LOW WORD COUNT INCORRECT SYNC RECEIVED PARITY / MANCHESTER ERROR RECEIVED RT-to-RT GAP / SYNC ADDRESS ERROR RT-to-RT NO RESPONSE ERROR RT-to-RT 2ND COMMAND WORD ERROR COMMAND WORD CONTENTS ERROR 15(MSB) TRANSMITTER TIMEOUT RT ADDRESS The Enhanced Mini-ACE/-ACE offers several different options for designating the Remote Terminal address. These include the following: (1) hardwired, by means of the 5 RT ADDRESS inputs, and the RT ADDRESS PARITY input; (2) by means of the RT ADDRESS (and PARITY) inputs, but latched via hardware, on the rising edge of the RT_AD_LAT input signal; (3) input by means of the RT ADDRESS (and PARITY) inputs, but latched via host software; and (4) software programmable, by means of an internal register. In all four configurations, the RT address is readable by the host processor. RT BUILT-IN-TEST (BIT) WORD The bit map for the Enhanced Mini-ACE/-ACE's internal RT Built-in-Test (BIT) Word is indicated in TABLE 42. RT AUTO-BOOT OPTION If utilized, the RT pin-programmable auto-boot option allows the Enhanced Mini-ACE/-ACE RT to automatically initialize as an active remote terminal with the Busy status word bit set to logic "1" immediately following power turn-on. This is a useful feature for MILSTD-1760 applications, in which the RT is required to be responding within 150 ms after power-up. This feature is available for versions of the Enhanced Mini-ACE/-ACE with 4K words of RAM. OTHER RT FEATURES The Enhanced Mini-ACE/-ACE includes options for the Terminal flag status word bit to be set either under software control and/or automatically following a failure of the loopback selftest. Other software programmable RT options include software programmable RT status and RT BIT words, automatic clearing of the Service Request bit following receipt of a Transmit vector word mode command, options regarding Data Word transfers for the Busy and Message error (illegal) Status word bits, and options for the handling of 1553A and reserved mode codes. For new applications, it is recommended that the selective message monitor mode be used, rather than the word monitor mode. Besides providing monitor filtering based on RT address, T/R bit, and subaddress, the message monitor eliminates the need to determine the start and end of messages by software. WORD MONITOR MODE In the Word Monitor Terminal mode, the Enhanced Mini-ACE/ACE monitors both 1553 buses. After the software initialization and Monitor Start sequences, the Enhanced Mini-ACE/-ACE stores all Command, Status, and Data Words received from both buses. For each word received from either bus, a pair of words is stored to the Enhanced Mini-ACE/-ACE's shared RAM. The first word is the word received from the 1553 bus. The second word is the Monitor Identification (ID), or "Tag" word. The ID word contains information relating to bus channel, word validity, and interword time gaps. The data and ID words are stored in a circular buffer in the shared RAM address space. WORD MONITOR MEMORY MAP A typical word monitor memory map is illustrated in TABLE 43. TABLE 43 assumes a 64K address space for the Enhanced MiniACE/-ACE's monitor. The Active Area Stack pointer provides the address where the first monitored word is stored. In the example, it is assumed that the Active Area Stack Pointer for Area A (location 0100) is initialized to 0000. The first received data word is stored in location 0000, the ID word for the first word is stored in location 0001, etc. The current Monitor address is maintained by means of a counter register. This value may be read by the CPU by means of the Data Stack Address Register. It is important to note that when the counter reaches the Stack Pointer address of 0100 or 0104, the initial pointer value stored in this shared RAM location will be overwritten by the monitored data and ID Words. When the internal counter reaches an address of FFFF (or 0FFF, for an 31 BU-6174X/6184X/6186X M-12/04-0 MONITOR ARCHITECTURE The Enhanced Mini-ACE/-ACE includes three monitor modes: (1) A Word Monitor mode (2) A selective message monitor mode (3) A combined RT/message monitor mode Data Device Corporation www.ddc-web.com TABLE 43. TYPICAL WORD MONITOR MEMORY MAP HEX ADDRESS 0000 0001 0002 0003 0004 005 * * * 0100 * * * FFFF FUNCTION First Received 1553 Word First Identification Word Second Received 1553 Word Second Identification Word Third Received 1553 Word Third Identification Word * * * Stack Pointer (Fixed Location - gets overwritten) * * * Received 1553 Words and Identification Word TABLE 44. MONITOR SELECTION TABLE LOOKUP ADDRESS BIT 15(MSB) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0(LSB) DESCRIPTION Logic "0" Logic "0" Logic "0" Logic "0" Logic "0" Logic "0" Logic "1" Logic "0" Logic "1" RTAD_4 RTAD_3 RTAD_2 RTAD_1 RTAD_0 TRANSMIT / RECEIVE SUBADDRESS 4 Enhanced Mini-ACE/-ACE with 4K RAM), the counter rolls over to 0000. WORD MONITOR TRIGGER In the Word Monitor mode, there is a pattern recognition trigger and a pattern recognition interrupt. The 16-bit compare word for both the trigger and the interrupt is stored in the Monitor Trigger Word Register. The pattern recognition interrupt is enabled by setting the MT Pattern Trigger bit in Interrupt Mask Register #1. The pattern recognition trigger is enabled by setting the Trigger Enable bit in Configuration Register #1 and selecting either the Start-ontrigger or the Stop-on-trigger bit in Configuration Register #1. The Word Monitor may also be started by means of a low-to-high transition on the EXT_TRIG input signal. tive monitor lookup table to determine if the particular command is enabled. The address for this location in the table is determined by means of an offset based on the RT Address, T/R bit, and Subaddress bit 4 of the current command word, and concatenating it to the monitor lookup table base address of 0280 (hex). The bit location within this word is determined by subaddress bits 3-0 of the current command word. If the specified bit in the lookup table is logic "0", the command is not enabled, and the Enhanced Mini-ACE/-ACE will ignore this command. If this bit is logic "1", the command is enabled and the Enhanced Mini-ACE/-ACE will create an entry in the monitor command descriptor stack (based on the monitor command stack pointer), and store the data and status words associated with the command into sequential locations in the monitor data stack. In addition, for an RT-to-RT transfer in which the receive command is selected, the second command word (the transmit command) is stored in the monitor data stack. The address definition for the Selective Monitor Lookup TABLE is illustrated in TABLE 44. SELECTIVE MESSAGE MONITOR MODE The Enhanced Mini-ACE/-ACE Selective Message Monitor provides monitoring of 1553 messages with filtering based on RT address, T/R bit, and subaddress with no host processor intervention. By autonomously distinguishing between 1553 command and status words, the Message Monitor determines when messages begin and end, and stores the messages into RAM, based on a programmable filter of RT address, T/R bit, and subaddress. The selective monitor may be configured as just a monitor, or as a combined RT/Monitor. In the combined RT/Monitor mode, the Enhanced Mini-ACE/-ACE functions as an RT for one RT address (including broadcast messages), and as a selective message monitor for the other 30 RT addresses. The Enhanced Mini-ACE/-ACE Message Monitor contains two stacks, a command stack and a data stack, that are independent from the RT command stack. The pointers for these stacks are located at fixed locations in RAM. SELECTIVE MESSAGE MONITOR MEMORY ORGANIZATION A typical memory map for the Enhanced Mini-ACE/-ACE in the Selective Message Monitor mode, assuming a 4K RAM space, is illustrated in TABLE 45. This mode of operation defines several fixed locations in the RAM. These locations are allocated in a way in which none of them overlap with the fixed RT locations. This allows for the combined RT/Selective Message Monitor mode. The fixed memory map consists of two Monitor Command Stack Pointers (locations 102 and 106 hex), two Monitor Data Stack BU-6174X/6184X/6186X M-12/04-0 MONITOR SELECTION FUNCTION Following receipt of a valid command word in Selective Monitor mode, the Enhanced Mini-ACE/-ACE will reference the selecData Device Corporation www.ddc-web.com 32 TABLE 45. TYPICAL SELECTIVE MESSAGE MONITOR MEMORY MAP (shown for 4K RAM for "Monitor only" mode) ADDRESS (HEX) 0000-0101 0102 0103 0104-0105 0106 0107 0108-027F 0280-02FF 0300-03FF 0400-07FF 0800-0FFF DESCRIPTION Not Used Monitor Command Stack Pointer A (fixed location) Monitor Data Stack Pointer A (fixed location) Not Used Monitor Command Stack Pointer B (fixed location) Monitor Data Stack Pointer B (fixed location) Not Used Selective Monitor Lookup Table (fixed location) Not Used Monitor Command Stack A Monitor Data Stack A half of the respective stack, while the Enhanced Mini-ACE/-ACE monitor writes messages to the lower half of the stack. Later, when the monitor issues a 100% stack rollover interrupt, the host can proceed to read the received data from the lower half of the stack, while the Enhanced Mini-ACE/-ACE monitor continues to write received data words to the upper half of the stack. INTERRUPT STATUS QUEUE Like the Enhanced Mini-ACE/-ACE RT, the Selective Monitor mode includes the capability for generating an interrupt status queue. As illustrated in FIGURE 11, this provides a chronological history of interrupt generating events. Besides the two Interrupt Mask Registers, the Interrupt Status Queue provides additional filtering capability, such that only valid messages and/or only invalid messages may result in entries to the Interrupt Status Queue. The interrupt status queue is 64 words deep, providing the capability to store entries for up to 32 monitored messages. Pointers (locations 103 and 107 hex), and a Selective Message Monitor Lookup Table (locations 0280 through 02FF hex). For this example, the Monitor Command Stack size is assumed to be 1K words, and the Monitor Data Stack size is assumed to be 2K words. FIGURE 12 illustrates the Selective Message Monitor operation. Upon receipt of a valid Command Word, the Enhanced MiniACE/-ACE will reference the Selective Monitor Lookup Table to determine if the current command is enabled. If the current command is disabled, the Enhanced Mini-ACE/-ACE monitor will ignore (and not store) the current message. If the command is enabled, the monitor will create an entry in the Monitor Command Stack at the address location referenced by the Monitor Command Stack Pointer, and an entry in the monitor data stack starting at the location referenced by the Monitor Data Stack Pointer. The format of the information in the data stack depends on the format of the message that was processed. For example, for a BC-to-RT transfer (receive command), the monitor will store the command word in the monitor command descriptor stack, with the data words and the receiving RT's status word stored in the monitor data stack. The size of the monitor command stack is programmable, with choices of 256, 1K, 4K, or 16K words. The monitor data stack size is programmable with choices of 512, 1K, 2K, 4K, 8K, 16K, 32K or 64K words. MISCELLANEOUS CLOCK INPUT The Enhanced Mini-ACE/-ACE decoder is capable of operating from a 10, 12, 16, or 20 MHz clock input. Depending on the configuration of the specific model Enhanced Mini-ACE/-ACE terminal, the selection of the clock input frequency may be chosen by one of either two methods. For all versions, the clock frequency may be specified by means of the host processor writing to Configuration Register #6. With the second method, which is applicable only for the versions incorporating 4K (but not 64K) words of internal RAM, the clock frequency may be specified by means of the input signals that are otherwise used as the A15 and A14 address lines. ENCODER/DECODERS For the selected clock frequency, there is internal logic to derive the necessary clocks for the Manchester encoder and decoders. For all clock frequencies, the decoders sample the receiver outputs on both edges of the input clock. By in effect doubling the decoders' sampling frequency, this serves to widen the tolerance to zero-crossing distortion, and reduce the bit error rate. For interfacing to fiber optic transceivers (e.g., for MIL-STD-1773 applications), the decoders are capable of operating with singleended, rather than double-ended, input signals. For applications involving the use of single-ended transceivers, it is suggested that you contact the factory at DDC regarding a transceiverless version of the Enhanced Mini-ACE. MONITOR INTERRUPTS Selective monitor interrupts may be issued for End-of-message and for conditions relating to the monitor command stack pointer and monitor data stack pointer. The latter, which are shown in FIGURE 10, include Command Stack 50% Rollover, Command Stack 100% Rollover, Data Stack 50% Rollover, and Data Stack 100% Rollover. The 50% rollover interrupts may be used to inform the host processor when the command stack or data stack is half full. At that time, the host may proceed to read the received messages in the upper Data Device Corporation www.ddc-web.com 33 TIME TAG The Enhanced Mini-ACE/-ACE includes an internal read/writable Time Tag Register. This register is a CPU read/writable 16-bit counter with a programmable resolution of either 2, 4, 8, 16, 32, or 64 s per LSB. Another option allows software controlled incrementing of the Time Tag Register. This supports self-test for the Time Tag Register. For each message processed, the value of the Time Tag Register is loaded into the BU-6174X/6184X/6186X M-12/04-0 second location of the respective descriptor stack entry ("TIME TAG WORD") for both the BC and RT modes. The functionality involving the Time Tag Register that's compatible with ACE/Mini-ACE (Plus) includes: the capability to issue an interrupt request and set a bit in the Interrupt Status Register when the Time Tag Register rolls over FFFF to 0000; for RT mode, the capability to automatically clear the Time Tag Register following reception of a Synchronize (without data) mode command, or to load the Time Tag Register following a Synchronize (with data) mode command. Additional time tag features supported by the Enhanced MiniACE/-ACE include the capability for the BC to transmit the contents of the Time Tag Register as the data word for a Synchronize (with data) mode command; the capability for the RT to "filter" the data word for the Synchronize with data mode command, by only loading the Time Tag Register if the LSB of the received data word is "0"; an instruction enabling the BC Message Sequence Control engine to load the Time Tag Register with a specified value; and an instruction enabling the BC Message Sequence Control engine to write the value of the Time Tag Register to the General Purpose Queue. interrupt by reading the two Interrupt Status Registers, which provide the current state of interrupt events and conditions. The Interrupt Status Registers may be updated in two ways. In one interrupt handling mode, a particular bit in Interrupt Status Register #1 or #2 will be updated only if the event occurs and the corresponding bit in Interrupt Mask Register #1 or #2 is enabled. In the enhanced interrupt handling mode, a particular bit in one of the Interrupt Status Registers will be updated if the event/condition occurs regardless of the value of the corresponding Interrupt Mask Register bit. In either case, the respective Interrupt Mask Register (#1 or #2) bit is used to enable an interrupt for a particular event/condition. The Enhanced Mini-ACE/-ACE supports all the interrupt events from ACE/Mini-ACE (Plus), including RAM Parity Error, Transmitter Timeout, BC/RT Command Stack Rollover, MT Command Stack and Data Stack Rollover, Handshake Error, BC Retry, RT Address Parity Error, Time Tag Rollover, RT Circular Buffer Rollover, BC Message, RT Subaddress, BC End-of-Frame, Format Error, BC Status Set, RT Mode Code, MT Trigger, and End-of-Message. For the Enhanced Mini-ACE/-ACE's Enhanced BC mode, there are four user-defined interrupt bits. The BC Message Sequence Control Engine includes an instruction enabling it to issue these interrupts at any time. For RT and Monitor modes, the Enhanced Mini-ACE/-ACE architecture includes an Interrupt Status Queue. This provides a mechanism for logging messages that result in interrupt requests. Entries to the Interrupt Status Queue may be filtered such that only valid and/or invalid messages will result in entries on the queue. The Enhanced Mini-ACE/-ACE incorporates additional interrupt conditions beyond ACE/Mini-ACE (Plus), based on the addition MONITOR DATA STACKS INTERRUPTS The Enhanced Mini-ACE/-ACE series terminals provide many programmable options for interrupt generation and handling. The interrupt output pin (INT) has three software programmable modes of operation: a pulse, a level output cleared under software control, or a level output automatically cleared following a read of the Interrupt Status Register (#1 or #2). Individual interrupts are enabled by the two Interrupt Mask Registers. The host processor may determine the cause of the CONFIGURATION REGISTER #1 MONITOR COMMAND STACK POINTERS MONITOR COMMAND STACKS 15 13 0 CURRENT AREA B/A BLOCK STATUS WORD TIME TAG WORD CURRENT COMMAND WORD DATA BLOCK POINTER RECEIVED COMMAND WORD MONITOR DATA BLOCK #N MONITOR DATA BLOCK #N + 1 NOTE IF THIS BIT IS "0" (NOT SELECTED) NO WORDS ARE STORED IN EITHER THE COMMAND STACK OR DATA STACK. IN ADDITION, THE COMMAND AND DATA STACK POINTERS WILL NOT BE UPDATED. MONITOR DATA STACK POINTERS SELECTIVE MONITOR LOOKUP TABLES OFFSET BASED ON RTA4-RTA0, T/R, SA4 SELECTIVE MONITOR ENABLE (SEE NOTE) FIGURE 12. SELECTIVE MESSAGE MONITOR MEMORY MANAGEMENT Data Device Corporation www.ddc-web.com 34 BU-6174X/6184X/6186X M-12/04-0 of Interrupt Mask Register #2 and Interrupt Status Register #2. This is accomplished by chaining the two Interrupt Status Registers using the INTERRUPT CHAIN BIT (bit 0) in Interrupt Status Register #2 to indicate that an interrupt has occurred in Interrupt Status Register #1. Additional interrupts include "SelfTest Completed", masking bits for the Enhanced BC Control Interrupts, 50% Rollover interrupts for RT Command Stack, RT Circular Buffers, MT Command Stack, and MT Data Stack; BC Op Code Parity Error, (RT) Illegal Command, (BC) General Purpose Queue or (RT/MT) Interrupt Status Queue Rollover, Call Stack Pointer Register Error, BC Trap Op Code, and the four User-Defined interrupts for the Enhanced BC mode. If there is a failure of the protocol self-test, it is possible to access information about the first failed vector. This may be done by means of the Enhanced Mini-ACE/-ACE's upper registers (register addresses 32 through 63). Through these registers, it is possible to determine the self-test ROM address of the first failed vector, the expected response data pattern (from the ROM), the register or memory address, and the actual (incorrect) data value read from register or memory. The on-chip self-test ROM is 4K X 24. Note that the RAM self-test is destructive. That is, following the RAM self-test, regardless of whether the test passes or fails, the shared RAM is not restored to its state prior to this test. Following a failed RAM self-test, the host may read the internal RAM to determine which location(s) failed the walking pattern test. BUILT-IN TEST A salient feature of the Enhanced Mini-ACE/-ACE is its highly autonomous self-test capability. This includes both protocol and RAM self-tests. Either or both of these self-tests may be initiated by command(s) from the host processor. The protocol test consists of a comprehensive toggle test of the terminal's logic. The test includes testing of all registers, Manchester decoders, protocol logic, and memory management logs. This test is completed in approximately 32,000 clock cycles. That is, about 1.6 ms with a 20 MHz clock, 2.0 ms at 16 MHz, 2.7 ms at 12 MHz, and 3.2 ms at 10 MHz. There is also a separate built-in test for the Enhanced Mini-ACE/ACE's 4K X 16 or 64K X 16 shared RAM. This test consists of writing and then reading/verifying the two walking patterns "data = address" and "data = address inverted". This test takes 10 clock cycles per word. For an Enhanced Mini-ACE/-ACE with 4K words of RAM, this is about 2.0 ms with a 20 MHz clock, 2.6 ms at 16 MHz, 3.4 ms at 12 MHz, or 4.1 ms at 10 MHz. For an Enhanced Mini-ACE/-ACE with 64K words of RAM, this test takes about 32.8 ms with a 20 MHz clock, 40.1 ms at 16 MHz, 54.6 ms at 12 MHz, or 65.6 ms at 10 MHz. The Enhanced Mini-ACE/-ACE built-in protocol test is performed automatically at power-up. In addition, the protocol or RAM selftests may be initiated by a command from the host processor, via the START/RESET REGISTER. For RT mode, this may include the host processor invoking self-test following receipt of an Initiate self-test mode command. The results of the self-test are host accessible by means of the BIT status register. For RT mode, the result of the self-test may be communicated to the bus controller via bit 8 of the RT BIT word ("0" = pass, "1" = fail). Assuming that the protocol self-test passes, all of the register and shared RAM locations will be restored to their state prior to the self-test, with the exception of the 60 RAM address locations 0342-037D and the TIME TAG REGISTER. Note that for RT mode, these locations map to the illegalization lookup table for "broadcast transmit subaddresses 1 through 30" (non-mode code subaddresses). Since MIL-STD-1553 does not define these as valid command words, this section of the illegalization lookup table is normally not used during RT operation. The TIME TAG REGISTER will continue to increment during the self-test. Data Device Corporation www.ddc-web.com 35 RAM PARITY The BC/RT/MT version of the Enhanced Mini-ACE/-ACE is available with options of 4K or 64K words of internal RAM. For the 64K option, the RAM is 17 bits wide. The 64K X 17 internal RAM allows for parity generation for RAM write accesses, and parity checking for RAM read accesses. This includes host RAM accesses, as well as accesses by the Enhanced Mini-ACE's/-ACE's internal logic. When the Enhanced Mini-ACE/-ACE detects a RAM parity error, it reports it to the host processor by means of an interrupt and a register bit. Also, for the RT and Selective Message Monitor modes, the RAM address where a parity error was detected will be stored on the Interrupt Status Queue (if enabled). RELOCATABLE MEMORY MANAGEMENT LOCATIONS In the Enhanced Mini-ACE/-ACE's default configuration, there is a fixed area of shared RAM addresses, 0000h-03FF, that is allocated for storage of the BC's or RT's pointers, counters, tables, and other "non-message" data structures. As a means of reducing the overall memory address space for using multiple Enhanced Mini-ACE/-ACE's in a given system (e.g., for use with the DMA interface configuration), the Enhanced Mini-ACE/-ACE allows this area of RAM to be relocated by means of 6 configuration register bits. To provide backwards compatibility to ACE and Mini-ACE, the default for this RAM area is 0000h-03FFh. HOST PROCESSOR INTERFACE The Enhanced Mini-ACE/-ACE supports a wide variety of processor interface configurations. These include shared RAM and DMA configurations, straightforward interfacing for 16-bit and 8-bit buses, support for both non-multiplexed and multiplexed address/data buses, non-zero wait mode for interfacing to a processor address/data buses, and zero wait mode for interfacing (for example) to microcontroller I/O ports. In addition, with respect to the ACE/MiniACE, the Enhanced Mini-ACE provides two major improvements: (1) reduced maximum host access time for shared RAM mode; and (2) increased maximum DMA grant time for the transparent/DMA mode. The Enhanced Mini-ACE/-ACE's maximum host holdoff time (time prior to the assertion of the READYD handshake signal) has been significantly reduced. For ACE/Mini-ACE, this maximum holdoff time is 17 internal word transfer cycles, resulting in BU-6174X/6184X/6186X M-12/04-0 an overall holdoff time of approximately 4.6 s, using a 16 MHz clock. By comparison, using the Enhanced Mini-ACE/-ACE's ENHANCED CPU ACCESS feature, this worst-case holdoff time is reduced significantly, to a single internal transfer cycle. For example, when operating the Enhanced Mini-ACE/-ACE in its 16-bit buffered, non-zero wait configuration with a 16 MHz clock input, this results in a maximum overall host transfer cycle time of 632 ns for a read cycle, or 570 ns for a write cycle. In addition, when using the ACE or Mini-ACE in the transparent/DMA configuration, the maximum request-to-grant time, which occurs prior to an RT start-of-message sequence, is 4.0 s with a 16 MHz clock, or 3.5 s with a 12 MHz clock. For the Enhanced Mini-ACE/-ACE functioning as a MIL-STD-1553B RT, this time has been increased to 8.5 s at 10 MHz, 9 s at 12 MHz, 10 s at 16 MHz, and 10.5 s at 20MHz. This provides greater flexibility, particularly for systems in which a host has to arbitrate among multiple DMA requestors. By far, the most commonly used processor interface configuration is the 16-bit buffered, non-zero wait mode. This configuration may be used to interface between 16-bit or 32-bit microprocessors and an Enhanced Mini-ACE/-ACE. In this mode, only the Enhanced Mini-ACE/-ACE's internal 4K or 64K words of internal RAM are used for storing 1553 message data and associated "housekeeping" functions. That is, in this configuration, the Enhanced Mini-ACE/-ACE will never attempt to access memory on the host bus. FIGURE 13 illustrates a generic connection diagram between a 16-bit (or 32-bit) microprocessor and an Enhanced Mini-ACE/ACE for the 16-bit buffered configuration, while FIGURES 14 and 15, and associated tables illustrate the processor read and write timing respectively. CLOCK OSCILLATOR CLK IN +5V (3.3V) (NOTE 5) D15-D0 TX/RXA N/C A15-A12 55 CH. A A11-A0 TX/RXA 55 CPU ADDRESS LATCH (NOTE 1) ADDR_LAT TRANSPARENT/BUFFERED +5V 16/8_BIT +5V TRIGGER_SEL N/C N/C (NOTE 2) 55 TX/RXB MSB/LSB POLARITY_SEL CH. B HOST (NOTE 3) ZERO_WAIT Enhanced Mini-ACE/ -ACE TX/RXB 55 SELECT ADDRESS DECODER MEM/REG RD/WR CPU STROBE CPU ACKNOWLEDGE (NOTE 4) RD/WR STRBD READYD TAG_CLK +5V RTAD4-RTAD0 RTADP RT ADDRESS, PARITY RESET MSTCLR SSFLAG/EXT_TRIG CPU INTERRUPT REQUEST INT NOTES: 1. CPU ADDRESS LATCH SIGNAL PROVIDED BY PROCESSORS WITH MULTIPLEXED ADDRESS/DATA BUSES. FOR PROCESSORS WITH NON-MULTIPLEXED ADDRESS AND DATA BUSSES, ADDR_LAT SHOULD BE CONNECTED TO +5V. 2. IF POLARITY_SEL = "1", RD/WR IS HIGH TO READ, LOW TO WRITE. IF POLARITY_SEL = "0", RD/WR IS LOW TO READ, HIGH TO WRITE. 3. ZERO_WAIT SHOULD BE STRAPPED TO LOGIC "1" FOR NON-ZERO WAIT INTERFACE AND TO LOGIC "0" FOR ZERO WAIT INTERFACE. 4. CPU ACKNOWLEDGE PROCESSOR INPUT ONLY FOR NON-ZERO WAIT TYPE OF INTERFACE. 5. +3.3V POWER FOR BU-61743 / 61843 / 61864 ONLY FIGURE 13. HOST PROCESSOR INTERFACE - 16-BIT BUFFERED CONFIGURATION Data Device Corporation www.ddc-web.com 36 BU-6174X/6184X/6186X M-12/04-0 t5 CLOCK IN t1 SELECT (Note 2,7) t2 t6 t14 t18 STRBD (Note 2) MEM/REG (Note 3,4,7) t3 t7 VALID t8 RD/WR (Note 4,5) IOEN (Note 2,6) READYD (Note 6) ;; ;; ; ;; ;; ;; ;; ;; ; t10 t19 A15-A0 (Note 7,8,9) D15-D0 (Note 6) FIGURE 14. CPU READING RAM / REGISTER (16-BIT BUFFERED, NONZERO WAIT) NOTES: 1. 2. For the 16-bit buffered nonzero wait configuration, TRANSPARENT/BUFFERED must be connected to logic "0". ZERO_WAIT and DTREQ / 16/8 must be connected to logic "1". The inputs TRIGGER_SEL and MSB/LSB may be connected to either +5V or ground. SELECT and STRBD may be tied together. IOEN goes low on the first rising CLK edge when SELECT * STRBD is sampled low (satisfying t1) and the Enhanced Mini-ACE/-ACE's protocol/memory management logic is not accessing the internal RAM. When this occurs, IOEN goes low, starting the transfer cycle. After IOEN goes low, SELECT may be released high. MEM/REG must be presented high for memory access, low for register access. MEM/REG and RD/WR are buffered transparently until the first falling edge of CLK after IOEN goes low. After this CLK edge, MEM/REG and RD/WR become latched internally. The logic sense for RD/WR in the diagram assumes that POLARITY_SEL is connected to logic "1". If POLARITY_SEL is connected to logic "0", RD/WR must be asserted low to read. The timing for IOEN, READYD and D15-D0 assumes a 50 pf load. For loading above 50 pf, the validity of IOEN, READYD, and D15-D0 is delayed by an additional 0.14 ns/pf typ, 0.28 ns/pf max. The timing for A15-A0, MEM/REG and SELECT assumes that ADDR-LAT is connected to logic "1". Refer to Address Latch timing for additional details. The address bus A15-A0 is internally buffered transparently until the first rising edge of CLK after IOEN goes low. After this CLK edge, A15-A0 become latched internally. Setup time given for use in worst case timing calculations. None of the Enhanced Mini-ACE/-ACE input signals are required to be synchronized to the system clock. When SELECT and STRBD do not meet the setup time of t1, but occur during the setup window of an internal flip-flop, an additional clock cycle will be inserted between the falling clock edge that latches MEM/REG and RD/WR and the rising clock edge that latches the Address (A15-A0). When this occurs, the delay from IOEN falling to READYD falling (t11) increases by one clock cycle and the address hold time (t10) must be increased be one clock cycle. 3. 4. 5. 6. 7. 8. 9. Data Device Corporation www.ddc-web.com ;; ;; ;; ;; ;; ;; t11 t13 t15 t4 t9 t12 VALID VALID ; t17 t16 ; ; 37 BU-6174X/6184X/6186X M-12/04-0 TABLE FOR FIGURE 14. CPU READING RAM OR REGISTERS (SHOWN FOR 16-BIT, BUFFERED, NONZERO WAIT MODE) REF t1 t2 DESCRIPTION SELECT and STRBD low setup time prior to clock rising edge SELECT and STRBD low to IOEN low (uncontended access @ 20 MHz) (contended access, with ENHANCED CPU ACCESS = "0" @ 20 MHz) (contended access, with ENHANCED CPU ACCESS = "1" @ 20 MHz) (uncontended access @ 16 MHz) (contended access, with ENHANCED CPU ACCESS = "0" @ 16 MHz) (contended access, with ENHANCED CPU ACCESS = "1" s @ 16 MHz) (uncontended access @ 12 MHz) (contended access, with ENHANCED CPU ACCESS = "0" @ 12 MHz) (contended access, with ENHANCED CPU ACCESS = "1" @ 12 MHz) (uncontended access @ 10 MHz) (contended access, with ENHANCED CPU ACCESS = "0" @ 10 MHz) (contended access, with ENHANCED CPU ACCESS = "1" @ 10 MHz) t3 Time for MEM/REG and RD/WR to become valid following SELECT and STRBD low(@ 20 MHz) @ 16 MHz @ 12 MHz @ 10 MHz t4 Time for Address to become valid following SELECT and STRBD low (@ 20 MHz) @ 16 MHz @ 12 MHz @ 10 MHz t5 t6 t7 t8 t9 t10 t11 CLOCK IN rising edge delay to IOEN falling edge SELECT hold time following IOEN falling MEM/REG, RD/WR setup time prior to CLOCK IN falling edge MEM/REG, RD/WR hold time following CLOCK IN falling edge Address valid setup time prior to CLOCK IN rising edge Address hold time following CLOCK IN rising edge IOEN falling delay to READYD falling (@ 20 MHz) @ 16 MHz @ 12 MHz @ 10 MHz t12 Output Data valid prior to READYD falling (@ 20 MHz) @ 16 MHz @ 12 MHz @ 10 MHz t13 t14 t15 t16 t17 t18 t19 CLOCK IN rising edge delay to READYD falling READYD falling to STRBD rising release time STRBD rising edge delay to IOEN rising edge and READYD rising edge Output Data hold time following STRBD rising edge STRBD rising delay to output data tri-state STRBD high hold time from READYD rising CLOCK IN rising edge delay to output data valid 0 40 6 0 40 0 40 6 2 3, 4, 5, 7 3, 4, 5, 7 7, 8 7, 8, 9 6, 9 6, 9 6, 9 6, 9 6 6 6 6 6 0 10 30 30 30 135 235 285 21 33 54 71 40 30 0 40 150 250 300 165 265 315 NOTES 2, 9 2, 6 2, 6 2, 6 2, 6 2, 6 2, 6 2, 6 2, 6 2, 6 2, 6 2, 6 2, 6 3, 4, 5, 7 3, 4, 5, 7 3, 4, 5, 7 3, 4, 5, 7 5V LOGIC 3.3V LOGIC MIN 10 TYP MAX MIN 15 100 3.6 515 112 4.6 630 133 6.0 815 150 7.2 965 15 21 32 40 17 30 50 67 40 0 15 30 35 30 135 235 285 11 23 44 61 TYP MAX UNITS ns 105 3.6 520 117 4.6 635 138 6.0 820 155 7.2 970 10 16 27 35 12 25 45 62 40 ns s ns ns s ns ns s ns ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 150 250 300 165 265 315 ns ns ns ns ns ns ns ns 170 187.5 205 170 187.5 205 40 40 ns ns ns ns ns ns ns Data Device Corporation www.ddc-web.com 38 BU-6174X/6184X/6186X M-12/04-0 t6 CLOCK IN t1 SELECT (Note 2,7) t2 t7 t16 t18 STRBD (Note 2) MEM/REG (Note 3,4,7) t3 t8 VALID t9 RD/WR (Note 4,5) IOEN (Note 2,6) t14 t15 t4 t17 READYD A15-A0 (Note 6) t10 t12 VALID (Note 7,8,9,10) t5 t11 VALID (Note 9,10) D15-D0 t13 FIGURE 15. CPU WRITING RAM / REGISTER (16-BIT BUFFERED, NONZERO WAIT) NOTES: 1. For the 16-bit buffered nonzero wait configuration TRANSPARENT/BUFFERED must be connected to logic "0", ZERO_WAIT and DTREG / 16/8 must be connected to logic "1". The inputs TRIGGER_SEL and MSB/LSB may be connected to either +5V or ground. 2. SELECT and STRBD may be tied together. IOEN goes low on the first rising CLK edge when SELECT * STRBD is sampled low (satisfying t1) and the Enhanced Mini-ACE/-ACE's protocol/memory management logic is not accessing the internal RAM. When this occurs, IOEN goes low, starting the transfer cycle. After IOEN goes low, SELECT may be released high. MEM/REG must be presented high for memory access, low for register access. MEM/REG and RD/WR are buffered transparently until the first falling edge of CLK after IOEN goes low. After this CLK edge, MEM/REG and RD/WR become latched internally. The logic sense for RD/WR in the diagram assumes that POLARITY_SEL is connected to logic "1". If POLARITY_SEL is connected to logic "0", RD/WR must be asserted high to write. The timing for the IOEN and READYD outputs assume a 50 pf load. For loading above 50 pf, the validity of IOEN and READYD is delayed by an additional 0.14 ns/pf typ, 0.28 ns/pf max. The timing for A15-A0, MEM/REG, and SELECT assumes that ADDR-LAT is connected to logic "1". Refer to Address Latch timing for additional details. The address bus A15-A0 and data bus D15-D0 are internally buffered transparently until the first rising edge of CLK after IOEN goes low. After this CLK edge, A15-A0 and D15-D0 become latched internally. Setup time given for use in worst case timing calculations. None of the Enhanced Mini-ACE/-ACE input signals are required to be synchronized to the system clock. When SELECT and STRBD do not meet the setup time of t1, but occur during the setup time of an internal flip-flop, an additional clock cycle may be inserted between the falling clock edge that latches MEM/REG and RD/WR and the rising clock edge that latches the address (A15-A0) and data (D15-D0). When this occurs, the delay from IOEN falling to READYD falling (t14) increases by one clock cycle and the address and data hold time (t12 and t13) must be increased by one clock. 3. 4. 5. 6. 7. 9. 10 Data Device Corporation www.ddc-web.com 39 BU-6174X/6184X/6186X M-12/04-0 TABLE FOR FIGURE 15. CPU WRITING RAM OR REGISTERS (SHOWN FOR 16-BIT, BUFFERED, NONZERO WAIT MODE) REF t1 t2 DESCRIPTION SELECT and STRBD low setup time prior to clock rising edge SELECT and STRBD low to IOEN low (uncontended access @ 20 MHz) (contended access, with ENHANCED CPU ACCESS = "0" @ 20 MHz) (contended access, with ENHANCED CPU ACCESS = "1" @ 20 MHz) (uncontended access @ 16 MHz) (contended access, with ENHANCED CPU ACCESS = "0" @ 16 MHz) (contended access, with ENHANCED CPU ACCESS = "1" @ 16 MHz) (uncontended access @ 12 MHz) (contended access, with ENHANCED CPU ACCESS = "0" @ 12 MHz) (contended access, with ENHANCED CPU ACCESS = "1" @ 12 MHz) (uncontended access @ 10 MHz) (contended access, with ENHANCED CPU ACCESS = "0" @ 10 MHz) (contended access, with ENHANCED CPU ACCESS = "1" @ 10 MHz) t3 Time for MEM/REG and RD/WR to become valid following SELECT and STRBD low(@ 20 MHz) @ 16 MHz @ 12 MHz @ 10 MHz t4 Time for Address to become valid following SELECT and STRBD low (@ 20 MHz) @ 16 MHz @ 12 MHz @ 10 MHz t5 Time for data to become valid following SELECT and STRBD low (@ 20 MHz) @ 16 MHz @ 12 MHz @ 10 MHz t6 t7 t8 t9 t10 t11 t12 t13 t14 CLOCK IN rising edge delay to IOEN falling edge SELECT hold time following IOEN falling MEM/REG, RD/WR setup time prior to CLOCK IN falling edge MEM/REG, RD/WR setup time following CLOCK IN falling edge Address valid setup time prior to CLOCK IN rising edge Data valid setup time prior to CLOCK IN rising edge Address valid hold time prior to CLOCK IN rising edge Data valid hold time following CLOCK IN rising edge IOEN falling delay to READYD falling @ 20 MHz @ 16 MHz @ 12 MHz @ 10 MHz t15 t16 t17 t18 CLOCK IN rising edge delay to READYD falling READYD falling to STRBD rising release time STRBD rising delay to IOEN rising edge and READYD rising edge STRBD high hold time from READYD rising 6 10 7, 8, 9 9 6, 9 6, 9 6, 9 6, 9 6 6 2 3, 4, 5, 7 3, 4, 5, 7 7, 8 0 10 30 30 10 30 10 85 110 152 185 100 125 167 200 115 NOTES 2, 10 2, 6 2, 6 2, 6 2, 6 2, 6 2, 6 2, 6 2, 6 2, 6 2, 6 2, 6 2, 6 3, 4, 5, 7 3, 4, 5, 7 3, 4, 5, 7 3, 4, 5, 7 5V LOGIC 3.3V LOGIC MIN 10 TYP MAX MIN TYP MAX 15 100 3.6 465 112 4.6 565 133 6.0 732 150 7.2 865 15 21 32 40 17 30 50 67 37 50 70 87 40 0 15 35 35 15 30 15 85 100 115 140 182 215 40 40 10 105 3.6 470 117 4.6 570 138 6.0 737 155 7.2 870 10 16 27 35 12 25 45 62 32 45 65 82 40 UNITS ns ns s ns ns s ns ns s ns ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 140 110 125 182 152 167 215 185 200 40 30 Data Device Corporation www.ddc-web.com 40 BU-6174X/6184X/6186X M-12/04-0 INTERFACE TO MIL-STD-1553 BUS FIGURE 16 illustrates the interface between the various versions of the Enhanced Mini-ACE/-ACE series and a MIL-STD-1553 bus. Connections for both direct (short stub) and transformer (long stub) coupling, as well as the nominal peak-to-peak voltage levels at various points (when transmitting), are indicated in the diagram. SHORT STUB (DIRECT COUPLED) (1:2.5) TX/RX 11.2 Vpp Enhanced Mini-ACE/-ACE TX/RX ISOLATION TRANSFORMER 55 28 Vpp 55 1 FT MAX 7 Vpp DATA BUS Z0 OR (1:1.79) LONG STUB (TRANSFORMER COUPLED) 20 FT MAX (1:1.41) 0.75 Z0 28 Vpp 11.2 Vpp Enhanced Mini-ACE/-ACE ISOLATION TRANSFORMER 20 Vpp 7 Vpp 0.75 Z0 COUPLING TRANSFORMER Z0 NOTES: 1. Z 0 = 70 TO 85 OHMS 2. NOMINAL VOLTAGE LEVELS SHOWN FIGURE 16. ENHANCED MINIATURE ADVANCED COMMUNICATIONS ENGINE INTERFACE TO MIL-STD-1553 BUS Data Device Corporation www.ddc-web.com 41 BU-6174X/6184X/6186X M-12/04-0 TRANSFORMERS In selecting isolation transformers to be used with the Enhanced Mini-ACE/-ACE, there is a limitation on the maximum amount of leakage inductance. If this limit is exceeded, the transmitter rise and fall times may increase, possibly causing the bus amplitude to fall below the minimum level required by MIL-STD-1553. In addition, an excessive leakage imbalance may result in a transformer dynamic offset that exceeds 1553 specifications. The maximum allowable leakage inductance is 6.0 H, and is measured as follows: The side of the transformer that connects to the Enhanced Mini-ACE/-ACE is defined as the "primary" winding. If one side of the primary is shorted to the primary center-tap, the inductance should be measured across the "secondary" (stub side) winding. This inductance must be less than 6.0 H. Similarly, if the other side of the primary is shorted to the primary center-tap, the inductance measured across the "secondary" (stub side) winding must also be less than 6.0 H. The difference between these two measurements is the "differential" leakage inductance.This value must be less than 1.0 H. Beta Transformer Technology Corporation (BTTC), a subsidiary of DDC, manufactures transformers in a variety of mechanical configurations with the required turns ratios of 1:2.5 direct coupled, and 1:1.79 transformer coupled. TABLE 46 provides a listing of many of these transformers. For further information, contact BTTC at 631-244-7393 or at www.bttc-beta.com. TABLE 46. BTTC TRANSFORMERS FOR USE WITH ENHANCED MINI-ACE TRANSFORMER CONFIGURATION Single epoxy transformer, through-hole, 0.625" X 0.625", 0.250" max height Single epoxy transformer, through-hole, 0.625" X 0.625", 0.220" max height. May be used with BU-6XXXXX4 versions of the Enhanced Mini-ACE. Single epoxy transformer, flat pack, 0.625" X 0.625", 0.275" max height Single epoxy transformer, surface mount, 0.625" X 0.625", 0.275" max height Single epoxy transformer, surface mount, hi-temp solder, 0.625" X 0.625", 0.220" max height. May be used with BU-6XXXXX4 versions of the Enhanced Mini-ACE Single epoxy transformer, flat pack, 0.625" X 0.625", 0.150" max height Single epoxy transformer, surface mount, 0.625" X 0.625", 0.150" max height Single epoxy transformer, through hole, transformer coupled only, 0.500" X 0.350", 0.250" max height Dual epoxy transformer, twin stacked, 0.625" X 0.625", 0.280" max height Dual epoxy transformer, twin stacked, surface mount, 0.625" X 0.625", 0.280" max height Dual epoxy transformer, twin stacked, flat pack, 0.625" X 0.625", 0.280" max height Dual epoxy transformer, side by side, through-hole, 0.930" X 0.630", 0.155" max height Dual epoxy transformer, side by side, flat pack, 0.930" X 0.630", 0.155" max height Dual epoxy transformer, side by side, surface mount, 0.930" X 0.630", 0.155" max height Dual epoxy transformer, side by side, surface mount, 1.410" X 0.750", 0.130" max height Single metal transformer, hermetically sealed, flat pack, 0.630" X 0.630", 0.175" max height Single metal transformer, hermetically sealed, surface mount, 0.630" X 0.630", 0.175" max height NOT RECOMMENDED BTTC PART NO. B-3067 B-3226 B-3818 B-3231 B-3227 B-3819 LPB-5014 LPB-5015 B-3229 TST-9007 TST-9017 TST-9027 TLP-1205 TLP-1105 TLP-1005 DLP-7115 (see note 3) HLP-6014 HLP-6015 DLP-7014 SLP-8007 SLP-8024 Notes: 1. For the BU-6XXXXX4 versions of the Enhanced Mini-ACE, which include the McAir-compatible transceivers, only the B-3818 or B-3819 transformers (shown in bold in the table) may be used. 2. For the BU-6XXXXX3 versions of the Enhanced Mini-ACE/-ACE with -1553B transceivers, any of the transformers listed in the table may be used. 3. DLP-7115 operates to +85C max. All other transformers listed operate to +130C max. Data Device Corporation www.ddc-web.com 42 BU-6174X/6184X/6186X M-12/04-0 THERMAL AND MECHANICAL MANAGEMENT FOR -ACE (BGA PACKAGE) Ball Grid Array (BGA) components necessitate that thermal management issues be considered early in the design stage for MIL-STD-1553 terminals. This is especially true if high transmitter duty cycles are expected. The temperature range specified for DDC's -ACE device refers to the temperature at the ball, not the case. All -ACE devices incorporate six package connections (E2, F2, G2, U13, U14, and U15), which perform the dual function of circuit ground and thermal heat sink. Refer to FIGURE 17 for connection locations. It is mandatory that these six balls be connected to a circuit ground plane (a circuit trace is insufficient) through thermal vias. Operation without an adequate ground/thermal plane is not recommended and extended exposure to these conditions may affect device reliability. The purpose of this ground/thermal plane is to conduct the heat being generated by the transceivers within the package and conduct this heat away from the -ACE. In general, the circuit ground and thermal (chassis) ground are not the same ground plane. It is acceptable for these six balls to be directly soldered to a ground plane but it must be located in close physical and thermal proximity ("0.003" pre-preg layer recommended) to the thermal plane. (USA) S/N D/C VU T R PNM L K J HG FE D CB A 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ESD and Pin 1 Identifier TOP VIEW BOTTOM VIEW Notes: 1) E2, F2, G2, U13, U14 and U15 must be connected to a thermal plane to maintain recommended operating temperature. FIGURE 17. THERMAL BALL LOCATIONS FOR -ACE (BGA PACKAGES) Data Device Corporation www.ddc-web.com 43 BU-6174X/6184X/6186X M-12/04-0 SIGNAL DESCRIPTIONS BY FUNCTIONAL GROUPS TABLE 47. POWER AND GROUND SIGNAL NAME BU-6186XFX/GX BU-6184XFX/GX BU-6174XFX/GX PIN +5V Vcc CH A +5V Vcc CH B +5V / +3.3V Logic 72 20 37 BU-61860BX BU-61840BX BU-61740BX BALL E1, F1, G1 V13, V14, V15 Channel A transceiver power. Channel B transceiver power. DESCRIPTION A8, A16, B8, L1, Logic power. For BU-61864/61843/61743, this pin must be connected to +3.3V. L2, L17, L18, B16 For BU-61865/61845/61745, this pin must be connected to +5V. For BU-61740/61840/61860BX, these eight balls may connect to either +5V or +3.3V. Refer to VDD_LOW (ball V2) signal information to determine voltage selection options. U3, V3 (BU-61860BX only) For BU-61864FX/GX, BU-61865FX/GX, and BU-61860BX this pin must be connected to +5V. Note: for BU-6184XFX/GX and BU-6174XFX/GX, this pin assumes the function UPADDREN. Note: for BU-61740BX and BU-61840BX, these two balls are not connected (N/C). +5V RAM 26 (BU-6186XFX/GX only) Ground 17, 18, 19, 65, 67 A9, B9, C17, C18, Ground. K17, K18, U4, U9, V1, V4 E2, F2, G2, U13, U14, U15 V2 Ground/Thermal connections. See Thermal and Mechanical Management Section for important user information. Input that selects logic threshold voltage. Set to logic "0" for 3.3V threshold and to +5V (logic "1") for 5V threshold. Must match "+5V/+3V Logic" input voltage. Ground/Thermal VDD_LOW (I) TABLE 48. 1553 ISOLATION TRANSFORMER SIGNAL NAME BU-6186XFX/GX BU-6184XFX/GX BU-6174XFX/GX PIN TX/RX-A (I/O) TX/RX-A (I/O) TX/RX-B (I/O) TX/RX-B (I/O) 5 7 13 16 BU-61860BX BU-61840BX BU-61740BX BALL D1, D2 H1, H2 U12, V12 U16, V16 Analog Transmit/Receive Input/Outputs. Connect directly to 1553 isolation transformers. DESCRIPTION Data Device Corporation www.ddc-web.com 44 BU-6174X/6184X/6186X M-12/04-0 TABLE 49. DATA BUS SIGNAL NAME BU-6186XFX/GX BU-6184XFX/GX BU-6174XFX/GX PIN D15 (MSB) D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) 53 50 48 49 52 54 51 46 47 36 45 39 44 43 38 42 BU-61860BX BU-61840BX BU-61740BX BALL D17 D18 J17 E18 E17 N17 N18 F18 F17 J18 H17 M18 G17 G18 M17 H18 16-bit bi-directional data bus. This bus interfaces the host processor to the Enhanced Mini-ACE/-ACE's internal registers and internal RAM. In addition, in transparent mode, this bus allows data transfers to take place between the internal protocol/memory management logic and up to 64K x 16 of external RAM. Most of the time, the outputs for D15 through D0 are in the high impedance state. They drive outward in the buffered or transparent mode when the host CPU reads the internal RAM or registers. Also, in the transparent mode, D15-D0 will drive outward (towards the host) when the protocol/management logic is accessing (either reading or writing) internal RAM, or writing to external RAM. In the transparent mode, D15-D0 drives inward when the CPU writes internal registers or RAM, or when the protocol/memory management logic reads external RAM. DESCRIPTION Data Device Corporation www.ddc-web.com 45 BU-6174X/6184X/6186X M-12/04-0 TABLE 50. PROCESSOR ADDRESS BUS SIGNAL NAME 64K RAM A15 4K RAM A15 / CLK_SEL_1 BU-6186XFX/GX BU-6184XFX/GX BU-6174XFX/GX PIN 66 BU-61860BX BU-61840BX BU-61740BX BALL A11 For BU-6186X (64K RAM versions), this signal is always configured as address line A15 (MSB). Refer to the description for A11A0 below. For BU-6184X/6174X (4K RAM versions), if UPADDREN is connected to logic "1", this signal operates as address line A15. For BU-6184X/6174X (4K RAM versions), if UPADDREN is connected to logic "0", this signal operates as CLK_SEL_1. In this case, A15/CLK_SEL_1 and A14/CLK_SEL_0 are used to select the Enhanced Mini-ACE/-ACE's clock frequency, as follows: Clock CLK_SEL_1 CLK_SEL_0 Frequency 0 0 10 MHz 0 1 20 MHz 1 0 12 MHz 1 1 16 MHz A14 A14 / CLK_SEL_0 8 B10 For BU-6186X (64K RAM versions), this signal is always configured as address line A14. Refer to the description of A11-A0 below. For BU-6184X/6174X (4K RAM versions), if UPADDREN is connected to logic "1", this signal operates as A14. For BU-6184X/6174X (4K RAM versions), if UPADDREN is connected to logic "0", then this signal operates as CLK_SEL_1. In this case, CLK_SEL_1 and CLK_SEL_0 are used to select the Enhanced Mini-ACE/-ACE's clock frequency, as defined in the description for A15/CLK_SEL1 above. A13 A13 / Vcc -LOGIC 71 A10 For BU-6186X (64K RAM versions), this signal is always configured as address line A13. Refer to the description for A11-A0 below. For BU-6184X/6174X (4K RAM versions), if UPADDREN is connected to logic "1", this signal operates as A13. For BU-6184X/6174X (4K RAM versions), if UPADDREN is connected to logic "0", then this signal MUST be connected to +5V/+3.3V-LOGIC (logic "1"). DESCRIPTION Data Device Corporation www.ddc-web.com 46 BU-6174X/6184X/6186X M-12/04-0 TABLE 50. PROCESSOR ADDRESS BUS (CONT.) SIGNAL NAME 64K RAM A12 4K RAM A12 / RTBOOT BU-6186XFX/GX BU-6184XFX/GX BU-6174XFX/GX PIN 70 BU-61860BX BU-61840BX BU-61740BX BALL A7 For BU-6186X (64K RAM versions), this signal is always configured as address line A12. Refer to the description for A11-A0 below. For BU-6184X/6174X (4K RAM versions), if UPADDREN is connected to logic "1", this signal operates as A12. For BU-6184X/6174X (4K RAM versions), if UPADDREN is connected to logic "0", then this signal functions as RTBOOT. If RTBOOT is connected to logic "0", the Enhanced Mini-ACE/-ACE will initialize in RT mode with the Busy status word bit set following power turn-on. If RTBOOT is hardwired to logic "1", the Enhanced Mini-ACE/-ACE will initialize in either Idle mode (for an RT-only part), or in BC mode (for a BC/RT/MT part). A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 (LSB) A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 (LSB) 3 4 69 6 11 22 68 9 10 12 27 15 B7 A6 B6 B5 A5 A4 B4 A3 B3 A2 B1 A1 Lower 12 bits of 16-bit bi-directional address bus. In both the buffered and transparent modes, the host CPU accesses the Enhanced Mini-ACE/-ACE registers and internal RAM by means of A11 - A0 (4K version). For the 64K versions, A15 - A12 are also used for this purpose. In buffered mode, A12-A0 (or A15-A0) are inputs only. In the transparent mode, A12-A0 (or A15-A0) are inputs during CPU accesses and become outputs, driving outward (towards the CPU) when the 1553 protocol/memory management logic accesses up to 64K words of external RAM. In transparent mode, the address bus is driven outward only when the signal DTACK is low (indicating that the Enhanced Mini-ACE/ACE has control of the RAM interface bus) and IOEN is high, indicating a non-host access. Most of the time, including immediately after power turn-on, A12-A0 (or A15-A0) will be in high impedance (input) state. DESCRIPTION Data Device Corporation www.ddc-web.com 47 BU-6174X/6184X/6186X M-12/04-0 TABLE 51. PROCESSOR INTERFACE CONTROL SIGNAL NAME BU-6186XFX/GX BU-6184XFX/GX BU-6174XFX/GX PIN SELECT (I) 61 BU-61860BX BU-61840BX BU-61740BX BALL B12 Generally connected to a CPU address decoder output to select the Enhanced MiniACE/-ACE for a transfer to/from either RAM or register. Strobe Data. Used in conjunction with SELECT to initiate and control the data transfer cycle between the host processor and the Enhanced Mini-ACE/-ACE. STRBD must be asserted low through the full duration of the transfer cycle. Read/Write. For a host processor access, RD/WR selects between reading and writing. In the 16-bit buffered mode, if POL_SEL is logic "0", then RD/WR should be low (logic "0") for read accesses and high (logic "1") for write accesses. If POL_SEL is logic "1", or the interface is configured for a mode other than 16-bit buffered mode, then RD/WR is high (logic "1") for read accesses and low (logic "0") for write accesses. Memory Output Enable or Address Latch. In buffered mode, the ADDR_LAT input is used to configure the buffers for A15-A0, SELECT, MEM/REG, and MSB/LSB (for 8-bit mode only) in latched mode (when low) or transparent mode (when high). That is, the Enhanced Mini-ACE/-ACE's internal transparent latches will track the values on A15-A0, SELECT, MEM/REG, and MSB/LSB when ADDR_LAT is high, and latch the values when ADDR_LAT goes low. In general, for interfacing to processors with a non-multiplexed address/data bus, ADDR_LAT should be hardwired to logic "1". For interfacing to processors with a multiplexed address/data bus, ADDR_LAT should be connected to a signal that indicates a valid address when ADDR_LAT is logic "1". In transparent mode, MEMOE output signal is used to enable data outputs for external RAM read cycles (normally connected to the OE input signal on external RAM chips). ZEROWAIT (I) / MEMWR (O) 23 U8 Memory Write or Zero Wait. In buffered mode, input signal (ZEROWAIT) used to select between the zero wait mode (ZEROWAIT = "0") and the non-zero wait mode (ZEROWAIT = "1"). In transparent mode, active low output signal (MEMWR) asserted low during memory write transfers to strobe data into external RAM (normally connected to the WR input signal on external RAM chips). 16 / 8 (I) / DTREQ (O) 24 V7 Data Transfer Request or Data Bus Select. In buffered mode, input signal 16/8 used to select between the 16 bit data transfer mode (16/8= "1") and the 8-bit data transfer mode (16/8 = "0"). In transparent mode (16-bit only), active low level output signal DTREQ used to request access to the processor/RAM interface bus (address and data buses). MSB / LSB (I) / DTGRT (I) 64 U6 Data Transfer Grant or Most Significant Byte/Least Significant Byte. In 8-bit buffered mode, input signal (MSB/LSB) used to indicate which byte is currently being transferred (MSB or LSB). The logic sense of MSB/LSB is controlled by the POL_SEL input. MSB/LSB is not used in the 16-bit buffered mode. In transparent mode, active low input signal (DTGRT) asserted in response to the DTREQ output to indicate that control of the external processor/RAM bus has been transferred from the host processor to the Enhanced Mini-ACE/-ACE. DESCRIPTION STRBD (I) 62 B14 RD / WR 63 A12 ADDR_LAT(I) / MEMOE (O) 14 V8 Data Device Corporation www.ddc-web.com 48 BU-6174X/6184X/6186X M-12/04-0 TABLE 51. PROCESSOR INTERFACE CONTROL (CONT.) SIGNAL NAME BU-6186XFX/GX BU-6184XFX/GX BU-6174XFX/GX PIN POL_SEL (I) / DTACK (O) 29 BU-61860BX BU-61840BX BU-61740BX BALL U7 Data Transfer Acknowledge or Polarity Select. In 16-bit buffered mode, if POL_SEL is connected to logic "1", RD/WR should be asserted high (logic "1") for a read operation and low (logic "0") for a write operation. In 16-bit buffered mode, if POL_SEL is connected to logic "0", RD/WR should be asserted low (logic "0") for a read operation and high (logic "1") for a write operation. In 8-bit buffered mode (TRANSPARENT/ BUFFERED = "0" and 16/8 = "0"), POL_SEL input signal used to control the logic sense of the MSB/LSB signal. If POL_SEL is connected to logic "0", MSB/LSB should be asserted low (logic "0") to indicate the transfer of the least significant byte and high (logic "1") to indicate the transfer of the most significant byte. If POL_SEL is connected to logic "1", MSB/LSB should be asserted high (logic "1") to indicate the transfer of the least significant byte and low (logic "0") to indicate the transfer of the most significant byte. In transparent mode, active low output signal (DTACK) used to indicate acceptance of the processor/RAM interface bus in response to a data transfer grant (DTGRT). The Enhanced Mini-ACE/-ACE's RAM transfers over A15-A0 and D15-D0 will be framed by the time that DTACK is asserted low. TRIG_SEL (I) / MEMENA_IN (I) 28 V6 Memory Enable or Trigger Select input. In 8-bit buffered mode, input signal (TRIG-SEL) used to select the order in which byte pairs are transferred to or from the Enhanced Mini-ACE/-ACE by the host processor. In the 8-bit buffered mode, TRIG_SEL should be asserted high (logic 1) if the byte order for both read operations and write operations is MSB followed by LSB. TRIG_SEL should be asserted low (logic 0) if the byte order for both read operations and write operations is LSB followed by MSB. This signal has no operation in the 16-bit buffered mode (it does not need to be connected). In transparent mode, active low input MEMENA_IN, used as a Chip Select (CS) input to the Enhanced Mini-ACE/-ACE's internal shared RAM. If only internal RAM is used, should be connected directly to the output of a gate that is OR'ing the DTACK and IOEN output signals. MEM / REG(I) 1 B13 Memory/Register. Generally connected to either a CPU address line or address decoder output. Selects between memory access (MEM/REG = "1") or register access (MEM/REG = "0"). Subsystem Flag (RT) or External Trigger (BC/Word Monitor) input. In RT mode, if this input is asserted low, the Subsystem Flag bit will be set in the Enhanced Mini-ACE/ACE's RT Status Word. If the SSFLAG input is logic "0" while bit 8 of Configuration Register #1 has been programmed to logic "1" (cleared), the Subsystem Flag RT Status Word bit will become logic "1", but bit 8 of Configuration Register #1, SUBSYSTEM FLAG, will return logic "1" when read. That is, the sense on the SSFLAG input has no effect on the SUBSYSTEM FLAG register bit. In the non-enhanced BC mode, this signal operates as an External Trigger input. In BC mode, if the external BC Start option is enabled (bit 7 of Configuration Register #1), a low to high transition on this input will issue a BC Start command, starting execution of the current BC frame. In the enhanced BC mode, during the execution of a Wait for External Trigger (WTG) instruction, the Enhanced Mini-ACE/-ACE BC will wait for a low-to-high transition on EXT_TRIG before proceeding to the next instruction. In the Word Monitor mode, if the external trigger is enabled (bit 7 of Configuration Register #1), a low to high transition on this input will initiate a monitor start. This input has no effect in Message Monitor mode. DESCRIPTION SSFLAG (I) / EXT_TRIG(I) 32 T2 Data Device Corporation www.ddc-web.com 49 BU-6174X/6184X/6186X M-12/04-0 TABLE 51. PROCESSOR INTERFACE CONTROL (CONT.) BU-6186XFX/GX BU-61860BX BU-6184XFX/GX BU-61840BX SIGNAL NAME BU-6174XFX/GX BU-61740BX PIN TRANSPARENT/ BUFFERED READYD 55 56 BALL B17 B15 Used to select between the buffered mode (when strapped to logic "0") and transparent/DMA mode (when strapped to logic "1") for the host processor interface. Handshake output to host processor. For a nonzero wait state read access, READYD is asserted at the end of a host transfer cycle to indicate that data is available to be read on D15 through D0 when asserted (low). For a nonzero wait state write cycle, READYD is asserted at the end of the cycle to indicate that data has been transferred to a register or RAM location. For both nonzero wait reads and writes, the host must assert STRBD low until READYD is asserted low. In the (buffered) zero wait state mode, this output is normally logic "1", indicating that the Enhanced Mini-ACE/-ACE is in a state ready to accept a subsequent host transfer cycle. In zero wait mode, READYD will transition from high to low during (or just after) a host transfer cycle, when the Enhanced Mini-ACE/-ACE initiates its internal transfer to or from registers or internal RAM. When the Enhanced Mini-ACE/-ACE completes its internal transfer, READYD returns to logic "1", indicating it is ready for the host to initiate a subsequent transfer cycle. IOEN(O) 58 A17 I/O Enable. Tri-state control for external address and data buffers. Generally not used in buffered mode. When low, indicates that the Enhanced Mini-ACE is currently performing a host access to an internal register, or internal or (for transparent mode) external RAM. In transparent mode, IOEN (low) should be used to enable external address and data bus tri-state buffers. DESCRIPTION TABLE 52. RT ADDRESS BU-6186XFX/GX BU-61860BX BU-6184XFX/GX BU-61840BX SIGNAL NAME BU-6174XFX/GX BU-61740BX PIN RTAD4 (MSB) (I) RTAD3 (I) RTAD2 (I) RTAD1 (I) RTAD0 (LSB) (I) RTADP 35 34 21 41 33 40 BALL T17 U18 U17 V18 V17 T18 If RT ADDRESS SOURCE is programmed to logic "1", then the Enhanced Mini-ACE/-ACE's source for its RT address and parity is under software control, via data lines D5-D0. In this case, the RTAD4-RTAD0 and RTADP signals are not used. Remote Terminal Address Parity. This input signal must provide an odd parity sum with RTAD4RTAD0 in order for the RT to respond to non-broadcast commands. That is, there must be an odd number of logic "1"s from among RTAD-4-RTAD0 and RTADP. RT Address Latch. Input signal used to control the Enhanced MINI-ACE/-ACE's internal RT address latch. If RT_AD_LAT is connected to logic "0", then the Enhanced Mini-ACE/-ACE RT is configured to accept a hardwired (transparent) RT address from RTAD4-RTAD) and RTADP. If RT_AD_LAT is initially logic "0", and then transitions to logic "1", the values presented on RTAD4-RTAD0 and RTADP will be latched internally on the rising edge of RT_AD_LAT. If RT_AD_LAT is connected to logic "1", then the Enhanced Mini-ACE/-ACE's RT address is latchable under host processor control. In this case, there are two possibilities: (1) If bit 5 of Configuration Register #6, RT ADDRESS SOURCE, is programmed to logic "0" (default), then the source of the RT Address is the RTAD4-RTAD0 and RTADP input signals; (2) If RT ADDRESS SOURCE is programmed to logic "1", then the source of the RT Address is the lower 6 bits of the processor data bus, D5-D1 (for RTAD4-0) and D0 (for RTADP). In either of these two cases (with RT_AD_LAT = "1"), the processor will cause the RT address to be latched by: (1) writing bit 15 of Configuration Register #3, ENHANCED MODE, to logic "1"; (2) writing bit 3 of Configuration Register #4, LATCH RT ADDRESS WITH CONFIGURATION REGISTER #5, to logic "1"; and (3) writing to Configuration Register #5. In the case of RT ADDRESS SOURCE = "1", then the values of RT address and RT address parity must be written to the lower 6 bits of Configuration Register #5, via D5-D0. In the case where RT ADDRESS SOURCE = "0", the bit values presented on D5-D0 become "don't care". RT Address inputs. If bit 5 of Configuration Register #6, RT ADDRESS SOURCE, is programmed to logic "0" (default), then the Enhanced Mini-ACE/-ACE's RT address is provided by means of these 5 input signals. In addition, if RT ADDRESS SOURCE is logic "0", the source of RT address parity is RTADP. There are many methods for using these input signals for designating the Enhanced MiniACE/-ACE's RT address. For details, refer to the description of RT_AD_LAT. DESCRIPTION RT_AD_LAT (I) 31 P18 Data Device Corporation www.ddc-web.com 50 BU-6174X/6184X/6186X M-12/04-0 TABLE 53. MISCELLANEOUS SIGNAL NAME BU-6186XFX/GX BU-6184XFX/GX BU-6174XFX/GX UPADDREN (BU-6174X, BU-6184X only) BU-61860BX BU-61840BX BU-61740BX UPADDREN BU-6186XFX/GX BU-6184XFX/GX BU-6174XFX/GX PIN 26 BU-61860BX BU-61840BX BU-61740BX BALL N2 For BU-61864/61865FX/GX, this pin signal is +5V-RAM and MUST be connected to +5V. For the 61860BX, this signal must be connected to logic "1". For BU-6174X and 6184X, this signal is used to control the function of the upper 4 address inputs (A15-A12). For these versions of Enhanced Mini-ACE/-ACE, if UPADDREN is connected to logic "1", then these four signals operate as address lines A15-A12. For BU-6184X/6174X, if UPADDREN is connected to logic "0", then A15 and A14 function as CLK_SEL_1 and CLK_SEL_0 respectively; A13 MUST be connected to Vcc-LOGIC (+5V or +3.3V); and A12 functions as RTBOOT. INCMD (O) / MCRST (O) 25 In-command or Mode Code Reset. The function of this pin is controlled by bit 0 of Configuration Register #7, MODE CODE RESET/INCMD SELECT. If this register bit is logic "0" (default), INCMD will be active on this pin. For BC, RT, or Selective Message Monitor modes, INCMD is asserted low whenever a message is being processed by the Enhanced Mini-ACE. In Word Monitor mode, INCMD will be asserted low for as long as the monitor is online. For RT mode, if MODE CODE RESET/INCMD SELECT is programmed to logic "1", MCRST will be active. In this case, MCRST will be asserted low for two clock cycles following receipt of a Reset remote terminal mode command. In BC or Monitor modes, if MODE CODE RESET/INCMD SELECT is logic "1", this signal is inoperative; i.e., in this case, it will always output a value of logic "1". INCMD (O) M1 For BC, RT, or Selective Message Monitor modes, INCMD is asserted low whenever a message is being processed by the -ACE. In Word Monitor mode, INCMD will be asserted low for as long as the monitor is online. For RT mode MCRST will be asserted low for two clock cycles following receipt of a Reset remote terminal mode command. Interrupt Request output. If the LEVEL/PULSE interrupt bit (bit 3) of Configuration Register #2 is logic "0", a negative pulse of approximately 500ns in width is output on INT to signal an interrupt request. If LEVEL/PULSE is high, a low level interrupt request output will be asserted on INT. The level interrupt will be cleared (high) after either: (1) The processor writes a value of logic "1" to INTERRUPT RESET, bit 2 of the Start/Reset Register; or (2) If bit 4 of Configuration Register #2, INTERRUPT STATUS AUTO-CLEAR is logic "1", then it will only be necessary to read the Interrupt Status Register (#1 and/or #2) that is requesting an interrupt that has been enabled by the corresponding Interrupt Mask Register. However, for the case where both Interrupt Status Register #1 and Interrupt Status Register #2 have bits set reflecting interrupt events, it will be necessary to read both interrupt status registers in order to clear INT. DESCRIPTION - MCRST (O) - A13 INT (O) INT (O) 57 A18 Data Device Corporation www.ddc-web.com 51 BU-6174X/6184X/6186X M-12/04-0 TABLE 53. MISCELLANEOUS (CONT.) SIGNAL NAME BU-6186XFX/GX BU-6184XFX/GX BU-6174XFX/GX CLOCK_IN (I) TX_INH_A (I) TX_INH_B (I) MSTCLR(I) BU-61860BX BU-61840BX BU-61740BX CLOCK_IN (I) TX_INH_A (I) TX_INH_B (I) MSTCLR(I) BU-6186XFX/GX BU-6184XFX/GX BU-6174XFX/GX PIN 30 59 60 2 BU-61860BX BU-61840BX BU-61740BX BALL V9 A14 A15 B11 20 MHz, 16 MHz, 12 MHz, or 10 MHz clock input. Transmitter inhibit inputs for the Channel A and Channel B MILSTD-1553 transmitters. For normal operation, these inputs should be connected to logic "0". To force a shutdown of Channel A and/or Channel B, a value of logic "1" should be applied to the respective TX_INH input. Master Clear. Negative true Reset input, normally asserted low following power turn-on. Time Tag Clock - External clock that may be used to increment the Time Tag Register. This option is selected by setting Bits 7, 8 and 9 of Configuration Register # 2 to Logic "1". If this input is set to logic "1", the Built-In-Self-Test (BIST) will be enabled after hardware reset (for example, following power-up). A logic "0" input disables both the power-up and user-initiated, automatic BIST. DESCRIPTION - TAG_CLK (I) - B18 - RSTBITEN (I) - P17 TABLE 54. NO USER CONNECTIONS SIGNAL NAME BU-6186XFX/GX BU-6184XFX/GX BU-6174XFX/GX NC BU-61860BX BU-61840BX BU-61740BX NC BU-6186XFX/GX BU-6184XFX/GX BU-6174XFX/GX PAD (*) P1, P2, P3, P4, P5, P6 BU-61860BX BU-61840BX BU-61740BX BALL B2, C1, C2, J1, No user connection J2, K1, K2, M2, N1, P1, P2, R1, R2, R17, R18, T1, U1, U2, U5, U10 U11, V5, V10, V11 DESCRIPTION (*) Note that the Test Output pins are recessed pads located on the bottom of the package. Data Device Corporation www.ddc-web.com 52 BU-6174X/6184X/6186X M-12/04-0 TABLE 55. ENHANCED MINI-ACE (FLAT PACK AND GULL WING PACKAGE) PINOUTS BU-61864(5) BC / RT / MT (64K RAM) MEM/REG MSTCLR A11 A10 TX/RX_A A8 TX/RX_A A14 A4 A3 A7 A2 TX/RX_B ADDR_LAT/MEMOE A0 TX/RX-B LOGIC GND LOGIC GND LOGIC GND +5V Vcc-CH. B RTAD2 A6 ZEROWAIT/MEMWR 8/16-BIT/DTREQ INCMD/MCRST +5V RAM A1 TRIG_SEL/MEMENA_IN POL_SEL/DTACK CLOCK_IN RT_AD_LAT SSFLAG/ EXT_TRIG RTAD0 RTAD3 RTAD4 D6 +5V/3.3V LOGIC BU-61843(5) BC / RT / MT, (4K RAM) BU-61743(5) RT ONLY, (4K RAM) MEM/REG MSTCLR A11 A10 TX/RX_A A8 TX/RX_A A14/CLK_SEL_0 A4 A3 A7 A2 TX/RX_B ADDR_LAT/MEMOE A0 TX/RX-B LOGIC GND LOGIC GND 55 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 LOGIC GND +5V Vcc-CH. B RTAD2 A6 ZEROWAIT/MEMWR 8/16-BIT/DTREQ INCMD/MCRST UPADDREN A1 TRIG_SEL/MEMENA_IN POL_SEL/DTACK CLOCK_IN RT_AD_LAT SSFLAG/ EXT_TRIG RTAD0 RTAD3 RTAD4 D6 +5V/3.3V LOGIC 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 BU-61864(5) BC / RT / MT (64K RAM) D1 D4 RTADP RTAD1 D0 D2 D3 D5 D8 D7 D13 D12 D14 D9 D11 D15 D10 TRANSPARENT/ BUFFERED READYD INT IOEN TX_INH_A TX_INH_B SELECT STRBD RD / WR MSB/LSB/DTGRT LOGIC GND A15 LOGIC GND A5 A9 A12 A13 +5V Vcc-CH. A BU-61843(5) BC / RT / MT, (4K RAM) BU-61743(5) RT ONLY, (4K RAM) D1 D4 RTADP RTAD1 D0 D2 D3 D5 D8 D7 D13 D12 D14 D9 D11 D15 D10 TRANSPARENT/ BUFFERED READYD INT IOEN TX_INH_A TX_INH_B SELECT STRBD RD / WR MSB/LSB/DTGRT LOGIC GND A15/CLK_SEL_1 LOGIC GND A5 A9 A12/RTBOOT A13/+5V/3.3V LOGIC +5V Vcc-CH. A PIN PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Data Device Corporation www.ddc-web.com 53 BU-6174X/6184X/6186X M-12/04-0 TABLE 56. ENHANCED MINI-ACE (FLAT PACK AND GULL WING) NO USER CONNECTIONS PAD (*) BU-6186XFX/GX BU-6184XFX/GX BU-6174XFX/GX NC NC NC NC NC P1 P2 P3 P4 P6 TABLE 57. -ACE (BGA PACKAGE) "DAISY CHAIN" MECHANICAL SAMPLE CONNECTIONS BALL PAIRS WIRED TOGETHER A1-A2 A3-A4 A5-A6 A7-A8 A9-A10 A11-A12 A13-A14 A15-A16 A17-A18 B1-B2 B3-B4 B5-B6 B7-B8 B9-B10 B11-B12 B13-B14 BALL PAIRS WIRED TOGETHER B15-B16 B17-B18 C1-C2 C17-C18 D1-D2 D17-D18 E1-E2 E17-E18 F1-F2 F17-F18 G1-G2 G17-G18 H1-H2 H17-H18 J1-J2 J17-J18 BALL PAIRS WIRED TOGETHER K1-K2 K17-K18 L1-L2 L17-L18 M1-M2 M17-M18 N1-N2 N17-N18 P1-P2 P17-P18 R1-R2 R17-R18 T1-T2 T17-T18 U1-U2 U3-U4 BALL PAIRS WIRED TOGETHER U5-U6 U7-U8 U9-U10 U11-U12 U13-U14 U15-U16 U17-U18 V1-V2 V3-V4 V5-V6 V7-V8 V9-V10 V11-V12 V13-V14 V15-V16 V17-V18 Data Device Corporation www.ddc-web.com 54 BU-6174X/6184X/6186X M-12/04-0 TABLE 58. -ACE (BGA PACKAGE) PINOUTS BALL A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 C1 C2 C17 C18 D1 D2 D17 D18 SIGNAL A0 A2 A4 A6 A7 A10 A12** or A12/RTBOOT*** +5V/3.3V LOGIC GND A13** or A13/Vcc_LOGIC*** A15** or A15/CLK_SEL_1*** RD/WR MCRST TX_INH_A TX_INH_B +5V/3.3V LOGIC IOEN INT A1 NC A3 A5 A8 A9 A11 +5V/3.3V LOGIC GND A14** or A14/CLK_SEL_0*** MSTCLR SELECT MEM/REG STROBE READY +5V/3.3V LOGIC TRANS/BUFFERED TAG_CLK NC NC GND GND TX/RX_A TX/RX_A D15 D14 BALL E1 E2 E17 E18 F1 F2 F17 F18 G1 G2 G17 G18 H1 H2 H17 H18 J1 J2 J17 J18 K1 K2 K17 K18 L1 L2 L17 L18 M1 M2 M17 M18 N1 N2 N17 N18 P1 P2 P17 P18 R1 R2 R17 R18 SIGNAL +5V_A GND/THERMAL* D11 D12 +5V_A GND/THERMAL* D7 D8 +5V_A GND/THERMAL* D3 D2 TX/RX_A TX/RX_A D5 D0 NC NC D13 D6 NC NC GND GND +5V/3.3V LOGIC +5V/3.3V LOGIC +5V/3.3V LOGIC +5V/3.3V LOGIC INCMD NC D1 D4 NC UPADDRENA D10 D9 NC NC RSTBITEN RT_AD_LAT NC NC NC NC BALL T1 T2 T17 T18 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 SIGNAL NC SSFLAG/EXT_TRIG RTAD4 RTADP NC NC VDD_RAM ( +5V) GND NC MSB/LSB/DTGRT POL_SEL/DTACK ZEROWAIT/MEMWR GND NC NC TX/RX_B GND/THERMAL* GND/THERMAL* GND/THERMAL* TX/RX_B RTAD2 RTAD3 GND VDD_LOW VDD_RAM (+5V) GND NC TRIG_SEL/MEMENA_IN 16/8 / DTREQ ADDR_LAT/MEMOE CLOCK IN NC NC TX/RX_B +5V_B +5V_B +5V_B TX/RX_B RTAD0 RTAD1 * See Thermal Management Section for important user information. ** Applicable for 64K RAM option. *** Applicable for 4K RAM option. Data Device Corporation www.ddc-web.com 55 BU-6174X/6184X/6186X M-12/04-0 TABLE 59. BU-61860E3 EVALUATION BOARD PINOUT (MADE FROM 128-BALL, MICRO-ACE BU-61860B3 BC/RT/MT 64K RAM) P1 PIN # 1 2 3 4 5 6 7 8 9 DEVICE BALL # A6 B7 B13 B5 A1 B3 A2 A5 B10 A9,B9,C17,C18,E2, F2,G2,K17,K18,U4, U9,U13,U14,U15, V1,V4 A9,B9,C17,C18,E2, F2,G2,K17,K18,U4, U9,U13,U14,U15, V1,V4 A9,B9,C17,C18,E2, F2,G2,K17,K18,U4, U9,U13,U14,U15, V1,V4 A10 A3 B6 A7 A11 B4 A12 U6 A8,A16,B8,B16,L1,L 2,L17,L18,U3,V3 A8,A16,B8,B16,L1,L 2,L17,L18,U3,V3 B14 -B12 A15 A17 A14 B15 A18 B18 B17 FUNCTION A10 A11 MEM/REG A08 A00 A03 A02 A07 A14 6 GND A9,B9,C17,C18,E2, F2,G2,K17,K18,U4, U9,U13,U14,U15, V1,V4 5 P2 PIN # 1 2 3 4 DEVICE BALL # ----A9,B9,C17,C18,E2, F2,G2,K17,K18,U4, U9,U13,U14,U15, V1,V4 FUNCTION DIR_TX/RX_B DIR_TX/RX_B STUB_TX/RX_B STUB_TX/RX_B GND GND 10 7 GND 8 9 10 GND 11 12 A13 A04 A09 A12 A15 A05 RD/WR MSB/LSB/DTGRT +5.0V_Logic 19 13 14 15 16 17 18 ------E1,F1,G1 E1,F1,G1 ----A9,B9,C17,C18,E2, F2,G2,K17,K18,U4, U9,U13,U14,U15, V1,V4 STUB_TX/RX_B STUB_TX/RX_B DIR_TX/RX_B DIR_TX/RX_B NC NC +5.0V Vcc CH A +5.0V Vcc CH A DIR_TX/RX_A DIR_TX/RX_A STUB_TX/RX_A STUB_TX/RX_A 11 12 13 14 15 16 17 18 19 20 21 GND 22 23 24 25 26 27 28 29 30 31 32 +5.0V_Logic 20 STRBD NC SELECT TX_INH_B IOEN TX_INH_A READYD INT TAG_CLK TRANS/BUFF 21 22 23 24 A9,B9,C17,C18,E2, F2,G2,K17,K18,U4, U9,U13,U14,U15, V1,V4 ----- GND STUB_TX/RX_A STUB_TX/RX_A DIR_TX/RX_A DIR_TX/RX_A Data Device Corporation www.ddc-web.com 56 BU-6174X/6184X/6186X M-12/04-0 TABLE 59. BU-61860E3 EVALUATION BOARD PINOUT (MADE FROM 128-BALL, MICRO-ACE BU-61860B3 BC/RT/MT 64K RAM) (CONT.) P3 PIN # 1 2 DEVICE BALL # N2 V8 A9,B9,C17,C18,E2, F2,G2,K17,K18,U4, U9,U13,U14,U15, V1,V4 V2 A8,A16,B8,B16,L1, L2,L17,L18,U3,V3 A8,A16,B8,B16,L1, L2,L17,L18,U3,V3 A9,B9,C17,C18,E2, F2,G2,K17,K18,U4, U9,U13,U14,U15, V1,V4 A9,B9,C17,C18,E2, F2,G2,K17,K18,U4, U9,U13,U14,U15, V1,V4 A9,B9,C17,C18,E2, F2,G2,K17,K18,U4, U9,U13,U14,U15, V1,V4 -U17 A9,B9,C17,C18,E2, F2,G2,K17,K18,U4, U9,U13,U14,U15, V1,V4 B11 V9 A9,B9,C17,C18,E2, F2,G2,K17,K18,U4, U9,U13,U14,U15, V1,V4 A4 U8 V7 A8,A16,B8,B16,L1, L2,L17,L18,U3,V3 A8,A16,B8,B16,L1, L2,L17,L18,U3,V3 V13,V14,V15 V13,V14,V15 M1 B1 V6 FUNCTION UPADDREN ADDR_LAT/MEMOE P3 PIN # 26 27 28 GND 29 30 VDD_LOW +5.0V_Logic 31 32 P4 PIN # 1 2 3 GND 4 5 6 GND 7 8 9 GND 10 11 10 11 NC RTAD2 12 GND 13 MSTCLR CLOCK_IN 15 GND 16 17 A06 ZEROWAIT/MEMWR 16/8/DTREQ +5.0V_Logic 18 19 20 21 22 +5.0V_Logic +5.0V Vcc CH B +5.0V Vcc CH B INCMD A01 TRIG_SEL/MEMENA_IN 23 24 DEVICE BALL # U7 P18 T2 V17 U18 -T17 DEVICE BALL # J18 P17 M18 M17 V18 T18 G18 H18 H17 G17 A9,B9,C17,C18,E2,F2, G2,K17,K18,U4,U9, U13,U14,U15,V1,V4 A9,B9,C17,C18,E2,F2, G2,K17,K18,U4,U9, U13,U14,U15,V1,V4 FUNCTION POL_SEL/DTACK RT_AD_LAT SSFLAG/EXT_TRIG RTAD0 RTAD3 NC RTAD4 FUNCTION D06 RSTBITEN D04 D01 RTAD1 RTADP D02 D00 D05 D03 GND 3 4 5 6 +5.0V_Logic 7 8 9 GND 12 A8,A16,B8,B16,L1, L2,L17,L18,U3,V3 A8,A16,B8,B16,L1, L2,L17,L18,U3,V3 F18 F17 J17 E18 D18 N18 E17 D17 N17 A13 +5.0V_Logic 13 14 14 +5.0V_Logic D08 D07 D13 D12 D14 D09 D11 D15 D10 MCRST 15 16 17 18 19 20 21 22 23 24 25 Data Device Corporation www.ddc-web.com 57 BU-6174X/6184X/6186X M-12/04-0 2.000 0.015 (50.800 0.381) 1.000 SQ 0.010 (25.400 0.254) 0.500 0.005 (12.70 0.127) 0.200 0.005 (5.080 0.127) 0.100 DIA. (2.540) (see note 4) P6 P5 P2 P4 P1 P3 72 1 INDEX DENOTES PIN NO. 1 VIEW "A" VIEW "B" 0.850 0.008 (21.590 0.203) 0.018 0.002 0.050 0.005 (0.457 0.051) (1.270 0.127) VIEW "B" BOTTOM VIEW 0.010 0.002 (0.254 0.051) 0.130 MAX (3.30) 0.050 0.005 (1.270 0.127) 0.035 0.005 (0.889 0.127) VIEW "A" 1.024 0.014 NOM. (26.010 0.356) 0.040 0.004 (1.016 0.102) 0.090 0.010 (2.286 0.254) SIDE VIEW Notes: 1) Dimensions are in inches (mm). 2) Package Material: Alumina (AL2O3) 3) Lead Material: Kovar, Plated by 50 in. minimum nickel under 60 in. minimum gold. 4) There are 6 test pads located on the bottom of the package. These pads are recessed so as not to interfere when mounting the hybrid. There are no user connections to these pads. FIGURE 18. MECHANICAL OUTLINE DRAWING FOR ENHANCED MINI-ACE 72-LEAD FLAT PACK Data Device Corporation www.ddc-web.com BU-6174X/6184X/6186X M-12/04-0 58 1.38 0.02 (35.05 0.51) 1.00 SQ 0.01 (25.40 0.25) 0.19 Ref (4.83 Ref) 0.100 DIA. (2.540) (see note 4) P6 P5 P2 P4 P1 P3 72 1 VIEW "B" 0.850 0.008 (21.590 0.203) 0.018 0.002 0.050 0.005 (0.457 0.051) (1.270 0.127) VIEW "B" BOTTOM VIEW 0.08 MIN FLAT (2.03) INDEX DENOTES PIN NO. 1 0.012 R. MAX (0.305 R.) 0.010 0.002 (0.254 0.051) 0.050 0.005 (1.27 0.127) 0.130 MAX (3.30) VIEW "A" 1.024 0.014 NOM. (26.010 0.356) SIDE VIEW 0.05 MIN FLAT 0.006 -0.004,+0.010 (1.27) (0.152 -0.100,+ 0.254) 0.075 MAX FLAT (1.91) VIEW "A" 0.19 Ref (4.83 Ref) Notes: 1) Dimensions are in inches (mm). 2) Package Material: Alumina (AL2O3) 3) Lead Material: Kovar, Plated by 50 in. minimum nickel under 60 in. minimum gold. 4) There are 6 test pads located on the bottom of the package. These pads are recessed so as not to interfere when mounting the hybrid. There are no user connections to these pads. FIGURE 19. MECHANICAL OUTLINE DRAWING FOR ENHANCED MINI-ACE 72-PIN GULL WING PACKAGE Data Device Corporation www.ddc-web.com BU-6174X/6184X/6186X M-12/04-0 59 .815 [20.70] (MAX) SQUARE .670 [17.02] (TYP) 0.022 [0.56] DIA Sn/Pb BALL (128 PLACES) .065 [1.65] (TYP) 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VU T R PNM L K J HG FE D CB A 17 EQ.SP. .0394 [1.00] = .670 [17.02] (TOL NONCUM) (TYP) .0394 [1.00] (TYP) .065 [1.65] (TYP) Triangle denotes Ball A1 BOTTOM VIEW Cover Material Diallyl Phthalate (DAP) 0.120 [3.05] (MAX) FR4 P.C. Board .032 [0.81] (REF) SIDE VIEW Notes: 1) Dimensions are in inches (mm). 2) Cover material: Diallyl Phthalate (DAP). 3) Base material: FR4 PC board. 4) Ball material: SnPb. 5) Solder Ball Cluster to be centralized within .010 of outline dimensions. 6) The copper pads (128 places) on the bottom of the BGA package are .025" (0.635 mm) in diameter prior to processing. Final ball size is .022" (0.56 mm) after processing (typical). FIGURE 20. MECHANICAL OUTLINE DRAWING FOR -ACE 128-BALL BGA PACKAGE Data Device Corporation www.ddc-web.com 60 BU-6174X/6184X/6186X M-12/04-0 ORDERING INFORMATION FOR ENHANCED MINI-ACE (FLAT PACK AND "GULL WING" PACKAGES) BU-61XXXXX-XXXX Supplemental Process Requirements: S = Pre-Cap Source Inspection L = 100% Pull Test Q = 100% Pull Test and Pre-Cap Inspection K = One Lot Date Code W = One Lot Date Code and PreCap Source Y = One Lot Date Code and 100% Pull Test Z = One Lot Date Code, PreCap Source and 100% Pull Test Blank = None of the Above Test Criteria: 0 = Standard Testing 2 = MIL-STD-1760 Amplitude Compliant (not available with Voltage/Transceiver Option 4 "McAir compatible") Process Requirements: 0 = Standard DDC practices, no Burn-In 1 = MIL-PRF-38534 Compliant (note 2) 2 = B (note 1) 3 = MIL-PRF-38534 Compliant (note 2) with PIND Testing 4 = MIL-PRF-38534 Compliant (note 2) with Solder Dip 5 = MIL-PRF-38534 Compliant (note 2) with PIND Testing and Solder Dip 6 = B (note 1) with PIND Testing 7 = B (note 1) with Solder Dip 8 = B (note 1) with PIND Testing and Solder Dip 9 = Standard DDC Processing with Solder Dip, no Burn-In Temperature Range** / Data Requirements: 1 = -55C to +125C 2 = -40C to +85C 3 = 0C to +70C 4 = -55C to +125C with Variables Test Data 5 = -40C to +85C with Variables Test Data 6 = Custom Part (Reserved) 7 = Custom Part (Reserved) 8 = 0C to +70C with Variables Test Data Voltage / Transceiver Option: 3 = +5 Volts rise/fall times = 100 to 300 ns (-1553B) 4 = +5 Volts rise/fall times = 200 to 300 ns (-1553B and McAir compatible)(not available with Test Criteria option 2 "MIL-STD-1760 Amplitude Compliant") Package Type: F = 72-Lead Enhanced Mini-ACE Flat Pack G = 72-Lead Enhanced Mini-ACE "Gull Wing" (Formed Lead) Logic / RAM Voltage (for BU-6186X versions, 64K x 17K RAM voltage is always 5V) 3 = 3.3 Volt (Applicable only for BU-61743 and BU-61843) 4 = 3.3 and 5 Volt (Applicable only for BU-61864) 5 = 5 Volt Product Type: BU-6174 = RT only with 4K x 16 RAM BU-6184 = BC / RT / MT with 4K x 16 RAM BU-6186 = BC / RT / MT with 64K x 17 RAM Notes: 1. Standard DDC processing with burn-in and full temperature test. See table on next page. 2. MIL-PRF-38534 product grading is designated with the following dash numbers: Class H is a -11X, 13X, 14X, 15X, 41X, 43X, 44X, 45X Class G is a -21X, 23X, 24X, 25X, 51X, 53X, 54X, 55X Class D is a -31X, 33X, 34X, 35X, 81X, 83X, 84X, 85X Data Device Corporation www.ddc-web.com 61 BU-6174X/6184X/6186X M-12/04-0 ORDERING INFORMATION FOR -ACE (BGA PACKAGE) BU-61XX0B3-202 Test Criteria: 2 = MIL-STD-1760 Amplitude Compliant Process Requirements: 0 = Standard DDC practices, no Burn-In Temperature Range** / Data Requirements: 2 = -40C to +85C Voltage / Transceiver Option: 3 = +5 Volts rise / fall times = 100 to 300 ns (-1553B) Package Type: B = 128-Ball BGA Package Logic / RAM Voltage (for BU-61860 version, 64K x 17K RAM voltage is always 5V) 0 = 3.3 or 5 Volt logic Product Type: BU-6174 = RT only with 4K x 16 RAM BU-6184 = BC / RT / MT with 4K x 16 RAM BU-6186 = BC / RT / MT with 64K x 17 RAM ** Temperature Range applies to ball temperature. BU-61860B3-601 -ACE (128-ball BGA) mechanical sample, with "daisy chain" connections of alternating balls, for use in environmental (mechanical / thermal) integrity testing. ORDERING INFORMATION FOR +5V TRANSCEIVER EVALUATION BOARD BU-61860E3-300 Evaluation board intended to support customers who are interested in electrically connecting and evaluating the performance of +5.0V Enhanced Mini-ACE and/or +5.0V Micro-ACE series of products. STANDARD DDC PROCESSING FOR HYBRID AND MONOLITHIC HERMETIC PRODUCTS TEST INSPECTION SEAL TEMPERATURE CYCLE CONSTANT ACCELERATION BURN-IN MIL-STD-883 METHOD(S) 2009, 2010, 2017, and 2032 1014 1010 2001 1015 (note 1), 1030 (note 2) CONDITION(S) -- A and C C 3000g TABLE 1 Notes: 1. For Process Requirement "B*" (refer to ordering information), devices may be non-compliant with MILSTD-883, Test Method 1015, Paragraph 3.2. Contact factory for details. 2. When applicable. STANDARD DDC PROCESSING TEST INSPECTION TEMPERATURE CYCLE MIL-STD-883 METHOD(S) 2010, 2017, and 2032 1010 CONDITION(S) -- B Data Device Corporation www.ddc-web.com 62 BU-6174X/6184X/6186X M-12/04-0 The information in this data sheet is believed to be accurate; however, no responsibility is assumed by Data Device Corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. Specifications are subject to change without notice. Please visit our web site at www.ddc-web.com for the latest information. 105 Wilbur Place, Bohemia, New York, U.S.A. 11716-2482 For Technical Support - 1-800-DDC-5757 ext. 7771 Headquarters, N.Y., U.S.A. - Tel: (631) 567-5600, Fax: (631) 567-7358 Southeast, U.S.A. - Tel: (703) 450-7900, Fax: (703) 450-6610 West Coast, U.S.A. - Tel: (714) 895-9777, Fax: (714) 895-4988 United Kingdom - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264 Ireland - Tel: +353-21-341065, Fax: +353-21-341568 France - Tel: +33-(0)1-41-16-3424, Fax: +33-(0)1-41-16-3425 Germany - Tel: +49-(0)89-150012-11, Fax: +49-(0)89-150012-22 Japan - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689 World Wide Web - http://www.ddc-web.com (R) ST ERED DATA DEVICE CORPORATION REGISTERED TO ISO 9001:2000 FILE NO. A5976 M-12/04-0 63 PRINTED IN THE U.S.A. FI RM U REG I |
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